Inbound Message Interface

The PCIe Controller includes a dedicated interface for inbound messages. The inbound message interface is suitable for driving a message gathering FIFO (the PCIe Controller does not include this FIFO). You can place message-type decode logic to filter messages into different FIFOs, take specific action, or discard redundant messages, depending on the application needs.

The interface is synchronous to AXI_CLK and does not support back pressuring. It includes valid, start, and end strobes, as well as strobes to identify vendor-defined header and data. The message interface width is the same as the AXI master port data bus.

The message header always occupies 64 bits with an additional 64 bits for header bits [127:64] of a vendor-defined message.

Table 1. Message Header Bit Allocation
Bits	Bit Description	Header Stripe
255:128	Unused	0
127:64	Vendor Defined Message Header Page Request Messages: [127:120] Page Address [63:56] [119:112] Page Address [55:48] [111:104] Page Address [47:40] [103:96] Page Address [39:32] [95:88] Page Address [31:24] [87:80] Page Address [23:16] [79:76] Page Address [15:12] [75:67] Page Request Group Index [66] L bit (last request in PRG) [65] W bit (write access requested) [64] R bit (read access requested) For Page Request Group Response Messages: [127:112] Destination ID [111:108] Response code 0000b: Success 0001b: Invalid request 1110b to 0010b: Unused 1111b: Response failure [104:96] PRG Index Stop Marker Messages: [71:67] Marker type (expected value 5'b00000) [66] L bit (expected value 1'b1) [65] W bit [64] R bit Invalidation Request Messages: [127:112] Destination ID Invalidate Completion Messages: [127:112] Device ID [98:96] CC value [95:64] ITAG Vector For OBFF messages, [123:120] carries the OBFF message code. Other bits are unused. For LTR messages: [127:120] Snoop latency bits [7:0] [119:112] Snoop latency bits [15:8] [111:104] No-snoop latency bits [7:0] [103:96] No-snoop latency bits [15:8]	0
63:60	Unused	0
59:52	PCIe tag for normal messages For invalidation request messages: [56:52] -ITAG	0
51:36	If bit 32 (TPH present) is set to 1, this field has the steering tag. If bit 32 is cleared this field has the PCIe tag for the vendor-defined messages.	0
35:34	Processing hint	0
33	1: 16-bit steering tag 0: 8-bit steering tag	0
32	TPH Present	0
31:24	Message Code	0
23:8	Requester ID	0
6:4	Routing	0
3:1	Attributes	0
0	0: Normal vendor defined message	0