Wait for Outstanding Completions before Entry

The PCIe Controller can wait for outstanding completions by using the Low Power Debug and Control Register 1/ Enable Outstanding CPL Check field in the local management space. The PCIe Controller waits for outstanding packets from the client and PCIe link. The PCIe Controller can respond to normal L1 exit triggers while waiting for outstanding completions. This field is normally not required unless you wants to fine tune latency for completions.