Entering L1 via ASPM

ASPM L1 is an autonomous process; entry and exit happens without any user handshaking. You can enable or disable ASPM L1 by setting the Active State Power Management Control (bit [1]) in the Link Control and Status Register. The PCIe Controller automatically initiates entry into ASPM L1 if the TX side is idle (i.e., no TLPs from the client and no replay TLPs pending) for a programmable time period. SPM L1 entry operates as follows:

  1. When the link TX is idle, the endpoint PCIe Controller begins incrementing the ASPM L1 entry timer internally. If the client requests to transmit a TLP, the timer is immediately cleared.
  2. When the ASPM L1 entry timer reaches the programmed value in the ASPM L1 Entry Timeout Delay Register, the PCIe Controller checks whether sufficient credits are accumulated.
  3. The PCIe Controller blocks new TLPs and initiates ASPM L1 entry by sending PM_Active_State_Request_L1 DLLPs to its transmit lanes.
  4. The PCIe Controller continuously transmits the PM_Active_State_Request_L1 DLLP until it receives a response from the upstream device.
  5. The upstream device must immediately respond to the request with an acceptance (PM_Request_Ack) or rejection (PM_Active_State_Nak).
  6. If the upstream device rejects with a 'PM_Active_State_Nak message, the PCIe Controller aborts the ASPM L1 entry and continues to send TLPs normally.
  7. If the upstream device accepts with a PM_Request_Ack message, the PCIe Controller puts its TX into electrical idle and enters ASPM L1.
  8. The upstream device detects the electrical idle and puts its TX into electrical idle as well.
For the transition to ASPM L1 to occur:
  • Endpoints—You must enable ASPM L1 in the Link Control Register of all the enabled functions.
  • Endpoints—You must enable the L1 power state in the Link Control Register of the PCIe Controller's root port register set.

ASPM L1 entry timeout is programmable through the ASPM L1 Entry Timeout Delay Register local management register. The L1 Timeout[19:0] field contains the timeout value (in 16 ns units) for transitioning to the ASPM L1 power state. Setting it to 0 disables the transition to the ASPM L1 power state.