Command Supported Check

The PCIe Controller performs this check for Step Margin commands. When it receives a valid Step Margin command, the PCIe Controller further checks whether the Step Margin Offset is within the supported range. If a Step Margin command is unsupported, the PCIe Controller responds with NAK status in the Lane Margin Status Register. No error is flagged in LM registers in this case.

  • The Step Margin Timing check is: Check Margin Payload[5:0] <= MNumTimingSteps
  • The Step Margin Voltage check is: Check Margin Payload[6:0] <= MNumVoltageSteps