Reset Interface Signals
| Signal | Direction | Width | Clock Domain | Description |
|---|---|---|---|---|
| HOT_RESET_IN | Input | 1 | AXI_CLK |
When this input is asserted in root port mode, the PCIe Controller initiates a hot reset sequence on the PCIe link. The PCIe Controller
keeps the PCIe link in hot reset as long as this signal remains asserted.
When de-asserted, the PCIe Controller brings the PCIe link out of
hot reset and initiates link training.
|
| HOT_RESET_OUT | Output | 1 | AXI_CLK | The PCIe Controller asserts this output when a hot reset is received from the link in endpoint mode. This signal is an active-high output driven synchronous to AXI_CLK. |
| LINK_DOWN_RESET_OUT | Output | 1 | AXI_CLK | The PCIe Controller asserts this output when the LTSSM detects a link-down event (i.e., when the LINK_UP state variable goes to 0). This signal is an active-high output driven synchronous to AXI_CLK. It is asserted high for eight AXI_CLK clock cycles during a link down event. |
| PERST_N | Input | 1 | Async | Triggers a warm reset from the I/O pad. |
| RESET_REQ | Output | 1 | Async | When this signal is asserted, the PCIe Controller requests to trigger a warm or hot reset. Refer to Reset Handshake. |
| RESET_ACK | Input | 1 | Async | Assert this signal to indicate readiness and permission for a warm or hot reset. Refer to Reset Handshake. |