Interrupt Interface Signals

Table 1. Interrupt interface
Signal Direction Width Clock Domain Description
LOCAL_INTERRUPT Output 1 AXI_CLK Active-high local error and status register interrupt. Asserted until software clears the Local Error and Status Register.
INTERRUPT_SIDEBAND_​SIGNALS Output 28 AXI_CLK Signal that causes local interrupt as sideband. See Interrupt Sideband Signals.
INTA_IN Input 1 When the PCIe Controller is configured as an endpoint, the client uses this input to signal an interrupt from any of its PCI functions to the root port using legacy PCIs interrupts. This input corresponds to the PCI bus INTA. Asserting this signal causes the PCIe Controller to send an Assert_INTx message; de-asserting it causes the PCIe Controller to transmit a Deassert_INTx message.
INTB_IN Input 1 AXI_CLK When the PCIe Controller is configured as an endpoint, the client uses this input to signal an interrupt from any of its PCI functions to the root port using Legacy PCI Express Interrupt Delivery. This input corresponds to the PCI bus INTB. Asserting this signal causes the PCIe Controller to send an Assert_INTx message; de-asserting it causes the PCIe Controller to transmit a Deassert_INTx message.
INTC_IN Input 1 AXI_CLK When the PCIe Controller is configured as an endpoint, the client uses this inputs to signal an interrupt from any of its PCI functions to the root port using Legacy PCI Express Interrupt Delivery. This input corresponds to Ithe PCI bus INT. Asserting this signal causes the PCIe Controller to send an Assert_INTx message; de-asserting it causes the PCIe Controller to transmit a Deassert_INTx message.
INTD_IN Input 1 AXI_CLK When the PCIe Controller is configured as an endpoint, the client uses this inputs to signal an interrupt from any of its PCI functions to the root port using Legacy PCI Express Interrupt Delivery. This input corresponds to the PCI bus INTD. Asserting this signals causes the PCIe Controller to send an Assert_INTx message; de-asserting it causes the PCIe Controller to transmit a Deassert_INTx message.
INT_PENDING_STATUS Input 4 AXI_CLK When using legacy interrupts, this input indicates the PF interrupt pending status. The i input must be set when an interrupt is pending in function i.
MSI_PENDING_STATUS_IN Input 128 AXI_CLK These inputs provide the status of the MSI pending interrupts for the PFs from the client to the PCIe Controller. If the MSI Pending Status In Mode Select field is set to 1 in the Debug Mux Control 2 Register in local management space, these pin settings determine the value read from the MSI Pending Bits Register of the corresponding PF. Bits [31:0] belong to PF0 , bits [63:32] to PF1, and so on.
INT_ACK Output 1 AXI_CLK A pulse on this output indicates that the PCIe Controller has sent an Assert_INTx or Deassert_INTx message in response to a change in the state of one of the INTx inputs.
INTA_OUT Output 1 AXI_CLK When the PCIe Controller is configured as a root port, this output emulates the PCI legacy interrupt INTA. The PCIe Controller asserts an interrupt output when it has received an Assert_INTx message from the link, and deasserts it when it receives a Deassert_INTx message.
INTB_OUT Output 1 AXI_CLK When the PCIe Controller is configured as a root port, this output emulates the PCI legacy interrupt INTB. The PCIe Controller asserts an interrupt output when it has received an Assert_INTx message from the link, and deasserts it when it receives a Deassert_INTx message.
INTC_OUT Output 1 AXI_CLK When the PCIe Controller is configured as a root port, this output emulates the PCI legacy interrupt INTC. The PCIe Controller asserts an interrupt output when it has received an Assert_INTx message from the link, and deasserts it when it receives a Deassert_INTx message.
INTD_OUT Output 1 AXI_CLK When the PCIe Controller is configured as a root port, this output emulates the PCI legacy interrupt INTD. The PCIe Controller asserts an interrupt output when it has received an Assert_INTx message from the link, and deasserts it when it receives a Deassert_INTx message.