Interrupt Sideband Signals

These signals let you generate custom interrupt signals. You can OR required signals from this vector to form interrupt signals. These signals are already masked internally using the corresponding mask bits given in the local management space for each kind of error.

Table 1. Interrupt Sideband Signals
Bit	Description
0	AXI slave reorder SRAM ECC uncorrectable error.
1	AXI slave WFIFO SRAM ECC uncorrectable error.
2	AXI master RFIFO SRAM ECC uncorrectable error.
3	Replay RAM parity error.
4	PNP RX FIFO parity error.
5	Completion RX FIFO parity error.
6	PNP RX FIFO pverflow.
7	Completion RX FIFO pverflow.
8	Replay timeout.
9	Replay timer rollover.
10	PHY error.
11	Malformed TLP received.
12	Unexpected completion received.
13	Flow control error.
14	Completion timeout.
15	This bit is set when the host toggles the Hardware Autonomous Width Change bit in the Link Control Register through a configuration write.
16	Unmapped TC error.
17	Set when the MSI mask register value in the MSI capability register changes value in any of the PCIe Controller's functions.
18	Set whenever the MSI-X function mask register value in the MSI-X capability register changes in any of the PCIe Controller's functions.
19	Set whenever any bit in the MSI mask register is cleared in any of the PCIe Controller's functions.
20	Set whenever any bit in the MSI mask register is set in any of the PCIe Controller's functions.
21	Set whenever the MSI-X function mask register is cleared in any of the PCIe Controller's functions.
22	Set whenever the MSI-X function mask register is set in any of the PCIe Controller's functions.
23	Set when a NFTS timeout occurs during Rx_L0s exit.
24	Uncorrectable error detected in SC table state RAM protect module.
25	Uncorrectable error detected in SC table timer RAM protect module.
26	Uncorrectable error detected in SC table byte count RAM protect module.
27	Link equalization requests interrupt. Endpoint. Indicates that the PCIe Controller has detected a problem with equalization and automatically requests an equalization retry at the end of equalization. Root port: Reserved.