L1.1 Operation

The PCIe Controller enters L1.1 when L1.1 entry conditions are true and L1.2 entry conditions are false. The following diagram illustrates L1.1 entry and locally initiated exit process. CLIENT_REQ_EXIT_L1 represents all local exit triggers.

Attention: You can enable L1.1 in the Interface Designer (PCI Express block > Pins tab > Power Management sub-tab > PM L1.1 Substate Enable).
It is possible to enable/disable L1.1 with the APB interface, however, you must follow the rules described in L1 Substate Register Programming for the power transitions to work correctly.
Figure 1. L1.1 Entry and Locally Initiated Exit

When the conditions for entering the L1.1 substate are met, the L1 PM substates state machine first performs a handshake with the PHY using the PHY_ENT_L1_X and PHY_ACK_L1_X signals to prepare the PHY for the removal of the reference clock. Once the PHY has asserted PHY_ACK_L1_X, the PCIe Controller de-asserts CLKREQ_OUT_N. If the link partner also de-asserts its CLKREQ# output, the core clock becomes inactive and the PCIe Controller's CLKREQ_IN_N input is de-asserted. The L1 PM substates state machine transitions to L1.1 when CLKREQ_IN_N goes high.

Any local L1 substate exit triggers bring the PCIe Controller back to the L1.0 state. During exit, the PCIe Controller asserts CLKREQ_OUT_N to turn on the core clock, thereby asserting CLKREQ_IN_N. When CLKREQ_IN_N goes low, the L1 PM substates state machine performs another handshake with the PHY by de-asserting PHY_ENT_L1_X and waiting for the PHY to respond by de-asserting PHY_ACK_L1_X. This handshake is necessary to prepare the PHY for the re-activation of the reference clock. Once this handshake has been completed, the PHY transitions back to the L1.0 substate.

Figure 2. L1.1 Entry and Exit Initiated by Link Partner

The previous figure illustrates the operation when the link partner initiates the exit from L1. The PCIe Controller enters L1.1 from L1.0 when the entry conditions for L1.2 are not satisfied and the entry conditions for L1.1 are satisfied. After completing the PHY_ENT_L1_X/ PHY_ACK_L1_X handshake with the PHY, the PCIe Controller de-asserts CLKREQ_OUT_N. If the link partner also de-asserts its CLKREQ# output, the core clock becomes inactive and the PCIe Controller's CLKREQ_IN_N input is de-asserted, causing the L1 PM substates state machine to enter the L1.1 state.

The link partner initiates the transition of the link from the L1 state by asserting its CLKREQ# outputt, resulting in the assertion the PCIe Controller's CLKREQ_IN_N input. When CLKREQ_IN_N goes low, the L1 PM substates state machine prepares the PHY for exit from L1.1 by de-asserting PHY_ENT_L1_X and waiting for the PHY to de-assert PHY_ACK_L1_X. When this handshake is completed, the L1 PM substates state machine transitions to the L1.0 substate. Meanwhile, the assertion of CLKREQ# results in the core clock becoming active, which enables the LTSSM to move out of L1 into recovery.