Ordering Between Posted and Non-Posted Writes

The PCIe Controller ensures strict ordering between posted and non-posted writes on the AXI master write interface. All posted write requests are issued with the same TARGET_AXI_AWID so that they complete in order in the AXI subsystem.

When a non-posted write follows a posted write, the PCIe Controller ensures that all outstanding posted writes complete (i.e., TARGET_AXI_BVALID is received for all outstanding write transactions) before issuing the non-posted write. This process ensures that non-posted transactions are not processed before posted transactions.