Link Down and Reset

When the link goes down or is disabled or upon hot reset, the PCIe Controller internally generates a link down reset, which clears all of its internal state machines, timers, and control registers. In the PCIe defined configuration register space, all registers, except those that are sticky, are also reset upon link down reset.

The PCIe Controller's AXI interface handles the link down reset as follows:

  • When the PCIe Controller detects a link down reset, it seets the Link Down Indication Bit in the AXI register space.
  • The AXI interface responds to the client with a SLVERR response while the Link Down Indication Bit is set.
  • All write requests from the application (via the AXI slave interface) are consumed by the AXI interface and return a SLVERR response.
  • All read requests are completed with a generated zero data pattern and return SLVERR response.

Additionally, the PCIe Controller aserrts the LINK_DOWN_RESET_OUT output signal upon a link down event. Your user application can monitor this signal to know when there is a link down event. For example, the client may have to reset its own FIFO buffers, registers, or state machines when the link is down. Firmware should clear the Link Down Indication Bit to restart any valid traffic after the negative edge of LINK_DOWN_RESET_OUT.

The AXI address translation registers are not cleared upon link down reset. These registers hold their programmed values and you do not need to re-program them.

Note: Refer to "AXI Configuration Registers" in the Titanium PCIe® Controller Registers User Guide for the register descriptions.