Inbound PCIe to AXI Address Translation (Endpoint)

The PCIe Controller performs end point inbound PCIe to AXI address translation on memory and I/O TLPs. The PCIe Controller chooses which address translation registers to use for translation based on the BAR match of the incoming TLP. There are seven BARs per function in endpoint mode; therefore, there are seven sets of registers per function with each BAR having two 32-bit registers (addr0 and addr1). The address translation logic takes the upper bits from the endpoint inbound PCIe to AXI address translation registers and takes the lower bits from the inbound PCIe address to form the AXI address. The inbound BAR aperture determines the number of bits to pass from the inbound PCIe address to AXI.

Table 1. Endpoint Inbound PCIe to AXI Address Translation Registers for 1 BARWhere BAR is bar0, bar1, bar2, … bar7 and PF is pf0, pf1, pf2, ... pf21

Register Name	Bits	Allocation	Default Value
[PF]_ib_ep_[BAR]_addr1	31:0	Upper [63:32] bits of the AXI address.	32'd0
[PF]_ib_ep_[BAR]_addr0	31:0	Lower [31:8] bits of the AXI address.	32'd0