Physical Layer

Data arrives from the PIPE interface over one or more lanes. Each lane has a 32-bit interface and a clock frequency of 62, 125, 250, or 500 MHz depending on the link speed. The data flow happens as follows:
  1. The data is converted to the core clock domain.
  2. The PCIe Controller de-scrambles each lane's data independently.
  3. Logic checks the data to detect any link power state transitions.
  4. Tthe lanes are de-skewed using FIFOs that are aligned on SKP sequences. The lanes are aligned as a single unit.

Figure 1. RX PHY Layer

A frame decoder decodes the de-skewed data, removes the SOP/EOP framing delimiters from the packet, and aligns them on the internal data path. The frame decoder can handle varying link widths and all potential packet alignments on the lanes. The decoded data is sent to the data link layer with indicators for packet type and errors detected.

The PCIe Controller sends each lane's received data to the Link Training Receive State Machine, which detects and decodes any training sequences from the lane. Each state machine passes information extracted from the training sequences to the LTSSM.

On the TX side, data arrives from the data link layer over a 128-bit data path, plus sideband signals. A frame decoder adds SOP and EOP delimiters to the packets and aligns them on the lanes. The frame encoder can handle varying link widths and all legal packet alignments on the lanes.

Figure 2. TX PHY Layer

The PCIe Controller multiplexes outgoing packets from the frame encoder with training sequences generated by the LTSSM. The multiplexer disables the data path from the frame encoder during link training, and allows the LTSSM to control the lanes. Each lane has its own scrambler to scramble the data before sending it to the PIPE interface. The outgoing PIPE interface has 32 bits per lane for all speeds with a PIPE clock frequency of 62, 125, 250, or 500 MHz), which determines the link speed.