Power Management Interface Signals

Refer to Power Management for a description of the PCIe Controller's power management capabilities.

Table 1. Power Management interface
Signal	Direction	Width	Clock Domain	Description
CLIENT_REQ_EXIT_L1	Input	1	Asynchronous	This signal triggers an exit to L0 from L1 or from L1-substates. This signal can also block L1 entry in endpoint mode. The client can trigger an explicit L1 exit by asserting this signal. You can drive this signal from the PM_CLK, core clock, or AXI_CLK domains, depending on hyour configuration. It is synchronized inside the PCIe Controller before use.
CLIENT_REQ_EXIT_L2	Input	1	AXI_CLK	The client can only assert this input in the short interval of time after the link enters L2 and before the system is powered off. While the power and clocks are on, the client can assert this input to initiate an exit from L2.Idle detect.
REQ_PM_TRANSITION_L23_READY	Input	1	AXI_CLK	In the PCIe Controller is in endpoint mode, the client can assert this input to transition the PCIe Controller's power management state to L23_READY (see PCIe specifications chapter 5 for a detailed description of power management). This transition happens after the PCIe Controller's functions are in the D3 state and after the client has acknowledged the PME_Turn_Off message from the root rort. Asserting this input causes the link to transition to the L2 state and requires a power-on reset to resume operation. You can hardwire this signal to 0 if the link does not need to transition to L2. This input is not used in the root port mode.
POWER_STATE_CHANGE_ACK	Input	1	AXI_CLK	When it is ready to transition to the low-power state requested by the configuration write request, the client must assert this input for one clock cycle in response to the assertion of POWER_STATE_CHANGE_INTERRUPT. The client can keep this input high if it does not need to delay the return of the completions for the configuration write transactions causing power-state changes.
FUNCTION_POWER_STATE	Output	12	AXI_CLK	These outputs provide the current power state of the PFs. Bits [2:0] capture the power state of function 0, bits [5:3] capture that of function 1, and so on. The possible power states are: 000: D0_uninitialized 001: D0_active 010: D1 100: D3hot
PCIE_LINK_POWER_STATE	Output	4	AXI_CLK	Current power state of the PCIe link. 0001: L0 0010: L0s 0100: L1 1000: L2
POWER_STATE_CHANGE_INTERRUPT	Output	1	AXI_CLK	The PCIe Controller asserts this output when the power state of a PF or VF is changing to the D1 or D3 states by a write into its Power Management Control Register. The PCIe Controller keeps this output high until the client asserts the POWER_STATE_CHANGE_ACK input. While this signal is high, the the PCIe Controller will not return completions for any pending configuration read or write transactions it receives. The intent is to delay the completion for the configuration write transaction that caused the state change until the client is ready to transition to the low power state. When this signal is high, the function number associated with the configuration write transaction is provided on the POWER_STATE_CHANGE_FUNCTION_NUM[7:0] output. When the client asserts POWER_STATE_CHANGE_ACK, the new state of the function that underwent the state change is reflected on the PCIe Controller's FUNCTION_POWER_STATE (for PFs) or the VF_POWER_STATE (for VFs) outputs.
POWER_STATE_CHANGE_FUNCTION_NUM	Output	8	AXI_CLK	Number of the function for which a power state change occurred.
DPA_INTERRUPT	Output	4	AXI_CLK	The PCIe Controller generates a one clock cycle pulse on one of these outputs when a configuration write transaction writes into the Dynamic Power Allocation Control Register to modify the device's DPA power state. [0] A pulse indicates a DPA event for PF0. [1] A pulse indicates a DPA event for PF1 and so on. The endpoitnt's software running must read the corresponding function's DPA control register to determine the DPA substate requested by the host and set the device's power state of the device. These outputs are not active in root port mode.