AXI Slave Read Operation

An AXI read is a split transaction with independent address and data on the corresponding channels. The client must follow the master protocol for the read address and data channel as described in the AXI Specification v1.0. The PCIe Controller follows the slave protocol for the read address and data channel as described in the AXI specification v1.0.

Figure 1. AXI Slave Read Interface Waveform
When MASTER_AXI_ARLEN is not zero, MASTER_AXI_ARSIZE must be the maximum value (5).

The client starts a memory read operation by placing the read request parameters on the AXI slave read address channel and asserting the MASTER_AXI_ARVALID signal. The PCIe Controller responds to the request by asserting the MASTER_AXI_ARREADY signal for one clock cycle. The PCIe Controller might not be able to accept the request if it does not have adequate credit to transmit the request TLP on the link or if the split completion table is full.

When the data for a read request becomes available, the PCIe Controller transfers the data on the AXI slave read data channel. The PCIe Controller begins the transfer by placing the data word on the MASTER_AXI_RDATA bus and asserting the MASTER_AXI_RVALID signal. The completion is delivered as a single burst for each read request. In the first data transfer cycle, the PCIe Controller returns data on MASTER_AXI_RDATA bus aligned to the request address. It indicates the last data transfer cycle by asserting the MASTER_AXI_RLAST signal. The client can pace the data transfer by controlling the MASTER_AXI_RREADY input to the PCIe Controller. The PCIe Controller keeps each data word on the MASTER_AXI_RDATA bus until it samples the ready input high on a positive edge of the clock. The PCIe Controller will not terminate a burst for a read request on the AXI slave interface. It always satisfies the complete read request as indicated by the MASTER_AXI_ARLEN signal.

In root port, the AXI Slave interface initiates configuration and I/O read requests, which function in the same way as memory reads. These requests are distinguished from memory requests by the transaction-type field in the master read descriptor bus. The data returned in response to these requests is always four bytes long and is delivered aligned to the request address.