Control SKIP for Lane Margining at Receiver

The Step Margin Execution Status is updated when write committed is received from the PHY. The 2-bit status is derived as shown in the following tables.

Table 1. Control SKP Ordered Set FormatWhere N is 1 - 5.
Symbol Number Value Description
0 through (4*N - 1) AAh SKP Symbol. Symbol 0 is the SKP Ordered Set identifier.
4*N 78h SKP_END_CTL Symbol. Signifies the end of the Control SKP Ordered Set after three more symbols.
4*N + 1 00-FFh
Bit 7: Data Parity
Bit 6: First Retimer Data Parity
Bit 5: Second Retimer Parity
Bits [4:0]: Margin CRC [4:0]
4*N + 2 00-FFh
Bit 7: Margin Parity
Bit 6: Usage Model : Set to 0b to indicate RX Lane Margining
Bit [5:3]: Margin Type
Bits [2:0]: Receiver Number
4*N + 3 00-FFh Bits [7:0] : Margin Payload
Table 2. Control SKP during Root Port and Endpoint Mode
Types Root Port Mode Endpoint Mode
Control SKP TX The contents of the four control fields of the Lane Margin Control and Status Register in the downstream port are always shown in the identical fields in the transmitted Control SKP Ordered Sets. The Control SKIP is always transmitted with No Command.
Control SKP RX
The PCIe Controller checks the Margin CRC and Margin Parity in the received Control SKIP Ordered Sets. Any mismatch detected is reported in the Lane Error Status Register.
The contents of the Control SKP Ordered Set received in the downstream port is reflected in the corresponding status fields of the Lane Margin Control and Status Register in the downstream port if either of these conditions are met in the Lane Margin Control and Status Register:
  • Receiver number is 010b - 101b.
  • Receiver number is 000b, margin command is clear, rrror log is no command or Go to Normal Settings, and there are retimer(s) in the link.
The PCIe Controller checks the margin CRC and margin parity in the received Control SKIP Ordered Sets. Detected mismatches are reported in the Lane Error Status Register.
The contents of the Control SKIP Ordered Sets are ignored in endpoint mode.