L1 Power Substates

The PCI-SIG L1 Power Management Substates ECN defines an optional mechanism to reduce idle power in the L1 link state by defining L1 substates to facilitate removing power from the PHY, and clocks to the PCIe Controller. The L1 PM substates are enabled when the link enters L1 due to PCI power management or ASPM.

There are two L1 substates:
  • The L1.1 substate allows you to turn off clocks and most of the PHY power, but it requires the PHY to maintain common-mode voltages on the TX side.
  • The L1.2 substate enables further reduction in idle power by not requiring common-mode voltages to be maintained.
Both L1.1 and L1.2 states allow you to turn off the PHY's electrical idle detection circuitry.

The L1 PM substates use the CLKREQ# sideband signal to control the clocks. The CLKREQ# signal is an open-drain, active-low signal shared by the upstream and downstream ports, and either side can assert it by driving it low. This signal enables the clock generator. The core clock is turned off when both sides de-assert their CLKREQ# outputs.

The PCIe Controller has the CLKREQ_IN_N input and a CLKREQ_OUT_N output to implement the tri-state CLKREQ# pin. The CLKREQ_OUT_N output, when low, enables the tri-state driver driving the CLKREQ# pin, causing assertion of the shared signal. The port on the other side can also assert CLKREQ# by driving it low. The PCIe Controller monitors the state of this shared signal through the CLKREQ_IN_N input, as shown in the following figure.

Figure 1. L1 PM Substates Block Diagram

Because the core clock is turned off in the L1.1 and L1.2 substates, a separate power management clock (PM_CLK) drives the L1 PM substates state machine. This clock must always be active, regardless of the link's power state. There is no requirement on the relative phase of this clock with respect to the other PCIe Controller clocks.

The L1 PM substates state machine also provides the handshake signals PHY_ENT_L1_X and PHY_ACK_L1_X to prepare the local PHY for the removal of the reference clock. The state machine asserts the PHY_ENT_L1_X output in the L1.0 substate when it has determined that the conditions for transition to the L1.1 or L1.2 substates are met. It then waits for the PHY to assert PHY_ACK_L1_X before de-asserting CLKREQ_OUT_N and entering L1.1 or L1.2 substates. During L1.1 or L1.2 exit, the PCIe Controller de-asserts PHY_ENT_L1_X to the PHY and waits for the corresponding de-assertion of PHY_ACK_L1_X before transitioning to the L1.0 state. This step is required to ensure that the PHY is fully operational and the clocks are stable before entering L1.0. For the case of L1.2, the PHY handshake is performed while in the L1.2 exit substate.

Note: De-asserting PHY_ENT_L1_X changes the PHY state from the L1 substate to L1.0. Make sure that the PHY has a stable reference clock during the exit process.

The L1 PM substates state machine provides an output signal PHY_RX_ELEC_IDLE_DET_EN to inform the PHY when to enable its electrical idle detection circuits on the RX side. The PCIe Controller asserts this output in all states except when the L1 PM substates state machine is in the L1.1, L1.2.Entry, and L1.2.Idle substates.

The L1 PM substates state machine also provides an output signal PHY_TX_CMN_MODE_EN to enable common mode on the PHY TX. The PCIe Controller de-asserts this output when the L1 PM substates state machine is in the L2.Idle substate, and asserts it at all other times.