Functional Description
The following figure shows a high-level overview of the PCIe Controller. This topic provides an overview of the layers, which are described in detail later.
Physical Layer
On the physical layer's receive (RX) side, data arrives from the link over the PIPE interface. For all link speeds, each lane is de-scrambled independently. The data from the lanes is de-skewed to generate aligned data. The PCIe Controller decodes the aligned data and sends the packets to the data link layer.
On the physical layer's transmit (TX) side, data arrives from the data link layer over a single interface. The PCIe Controller formats the data into packets by appending SOP and EOP, and aligns it on the outgoing lanes. For all link speeds, the data from each lane is scrambled independently before being transmitted on the outgoing PIPE. The physical layer has one instance of the Link Training and Status State Machine.
Data Link Layer
The data link layer receives packet data from the physical layer's RX. A CRC checker checks the incoming packet LCRC. The PCIe Controller sends the LCRC-stripped data to the transaction layer. A separate state machine performs the data link layer initialization.
On the TX side, the data link layer receives packets from the transaction layer over a 128-bit data path. It then adds the LCRC to the packets, multiplexes them with other data link layer packets (such as ACKs and flow control DLLPs), and forwards them to the physical layer. The TX side of the data link layer also has the replay buffer that is required for re-transmitting packets.
Transaction Layer
At the transaction layer, data arrives on the RX side from the data link layer. The arriving packets go into a receive FIFO buffer, and packet forwarding only begins when the FIFO buffer has a complete packet. Packets are decoded and forwarded to the appropriate host interface, or to an internal module (for example, interrupt messages). The host interfaces include separate interfaces for posted/non-posted (PNP) and completion packets.
The TX side of the transaction layer receives data from the client logic through separate interfaces for each type (posted/non-posted and completion). A state machine processes the data, schedules the packets, and forwards them over a common data path to the data link layer.
AXI Application Layer
The application layer provides a simple interface to a host bus or DMA engine on the user side. The application layer has three separate interfaces to the user logic:
- Target memory read/write interface—Provides a straightforward interface to the user memory controller or DMA engine. This interface also delivers I/O requests and messages received from the link to the client. EPs need this interface.
- Master read/write interface—Lets an EP generate memory transactions to the host as bus master; an RP can generate memory, I/O, configuration, and message requests. Devices that require bus master capability need this interface, e.g., all RPs and EPs that have master capability.
- Interrupt interface—Communicates the interrupt state between the user application and the PCIe Controller.
The application interface can maintain the state of up to 256 non-posted transactions (memory reads, I/O reads and writes, configuration reads and writes) generated on the master side, allowing their completions to be matched to the requests.
PCIe Controller Configuration
Many of the PCIe Controller's interfaces and features are user configurable with the Efinity Interface Designer. The settings you make in the Interface Designer are the defaults that the PCIe Controller uses when you power it up or perform a cold reset. You can also change many of the settings via the APB interface (if you enable it).