Function-Level Reset (FLR)

FLR enables the user application to reset a specific function on the endpoint; the FLR only affects the targeted function. When a specific VF is reset, only that VF's resources are reset. When a PF is reset, all of the PF's resources, including those of its associated VFs, are reset. The link state is not affected by an FLR.

Note: Refer to Function-Level Reset Signals for a detailed description of the signals.

The following figure shows the handshake of FLR_DONE and FLR_IN_PROGRESS in PF3, and is applicable to any PFs/VFs undergoing FLR.

When the host sets the FLR bit in an endpoint function's device control register with a CfgWr, the PCIe Controller first responds with the completion. Then it initiates the FLR. The affected function's configuration registers are reset as described in the PCIe specification.

The PCIe Controller asserts the FLR_IN_PROGRESS and VF_FLR_IN_PROGRESS outputs to the user application, indicating the PFs and VFs that received a FLR.

When the PCIe Controller asserts FLR_IN_PROGRESS[n], the user application must clear any pending transactions associated with the function (PF/VF) being reset. Then, the user application must assert FLR_DONE[n] and hold FLR_DONE[n] high until the de-assertion of FLR_IN_PROGRESS[n]. At the same time, the associated PF/VF undergoes an internal re-programming and retrieves the original user configurations. Upon the assertion of FLR_DONE[n] from both ends (user and internal reprogramming), the PCIe Controller de-asserts FLR_IN_PROGRESS[n], at which time the user application must de-assert FLR_DONE[n].

Note: The client must complete the FLR within 100 ms, as required by the PCIe specification.

While the FLR_IN_PROGRESS and VF_FLR_IN_PROGRESS outputs are high, any configuration or memory or I/O requests the function receives are silently discarded as permitted by the PCIe specification.

Each function's Bus Master Enable bit in the Command Register is also reset upon FLR. The client can only restart outbound traffic after the host sets the Bus Master Enable bit through a CfgWr.

In the event of an FLR, requests on the AXI interface are handled as follows:

In progress write requests complete normally. The client should not initiate any additional write requests from the function under FLR.
Read requests from the affected function return SLVERR on RRESP.
The AXI address translation registers are not affected by FLR for any function.