| AER |
Advanced Error Reporting |
| ARI |
Alternative Routing-ID Interpretation |
| ASPM |
Active-state power management |
| AXI |
Advanced eXtensible Interface |
| EP |
Endpoint |
| PCIe |
Peripheral Component Interface Express |
| PNP |
Posted/Non-Posted |
| SOP |
Start Of Packet |
| EOP |
End Of Packet |
| CRC |
Cyclic Redundancy Check |
| LCRC |
Link Cyclic Redundancy Check |
| DLLP |
Data Link Layer Packet |
| LTSSM |
Link Training and Status State Machine |
| TLP |
Transaction Layer Packet |
| AER |
Advanced Error Reporting |
| FLR |
Function-Level Reset |
| PBA |
Pending Bit Array |
| MSI |
Message-Signaled Interrupt |
| OS |
Ordered Set |
| ASPM |
Active State Power Management |
| UR |
Unsupported request |
| LTR |
Latency Tolerance Reporting |
| PTM |
Precision Time Measurement |
| RP |
Root Port |
| OBFF |
Optimized Buffer Flush/Fill |
| IDO |
ID-based Ordering |
| VC |
Virtual Channel |
| Register notation |
| R |
Read Only for Software Root Complex. |
| RW |
The software can read or write. Write access to configuration registers through
the local management interface. |
| WOCLR |
Software has to write a 1 to clear. The PCIe Controller sets the bit
and software clears the bit. |
| R/WOCLR |
The software can read or write. The software has to write a 1 to clear. The PCIe Controller sets the bit and software clears the bit. |
| W |
Write Only Register Field. A read will return 00s. |