Entering L1 via PCI-PM

When the PCIe Controller is configured as an endpoint, the PCI power management operation is as follows:

  1. The PCIe Controller operates normally with all functions in the D0 active state.
  2. The remote root port writes to the Power Management Control Register for all enabled functions, which transitions the function(s) to the non-D0 power state.
  3. When all functions are in the non-D0 state, the PCIe Controller initiates a link power state transition to L1 by transmitting PM_Enter_L1 DLLPs.
  4. After the data link layer handshake, the link transitions to the L1 state.

While the link is in L1 state and the PCIe Controller's functions are in D1 or D3hot, the link partner can transition the link from L1 to L0 at any time. The PCIe Controller can then optionally initiate a re-entry back to L1 if the link has been idle for a set interval and the PCIe Controllers functions are still in D3hot. The re-entry to L1 is controlled by the delay programmed in the L1 State Re-entry Delay Register in the local management space. Setting this register to a non-zero value causes the PCIe Controller to initiate entry back to L1 when a delay equal to the number of clock cycles programmed in this register has elapsed with no link activity. Setting this register to 0 prevents re-entry to L1. The initial transition to L1 (step 3 above) is not affected by this register setting.