Zero Length Reads

The AXI master interface signals a zero-length memory read transaction as a normal read request with a burst size TARGET_AXI_ARLEN of 0. The client must respond to a zero-length request in the same manner as a one-cycle read request by transferring a dummy one-cycle read data burst. The PCIe Controller then sends a completion TLP with a one-DWORD payload and byte count set to 1, as required by the PCIe specification.