Command Processing (Root Port)

The following table shows how the PCIe Controller processes margining commands in root port mode.

Table 1. Command Processing in Roor Port Mode
Command (Margin Control Register) PIPE Interface Response (Margin Status Register)
No Command
Margin Type [2:0]: 111b
Receiver Number [2:0]: 000b
Margin Payload [7:0]: 9Ch
 No change
Margin Type [2:0]: 111b
Receiver Number [2:0]: 000b
Margin Payload [7:0]: 9Ch
Access Retimer Register
Margin Type [2:0]: 001b
Receiver Number [2:0]: 010b/100b
Margin Payload [7:0]: XXh
 No change
Command sent on Control SKP sent by downstream port.
Margin Status Updated from the Control SKP OS received by the downstream port.
Report Margin Control Capabilities
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b through 101b
Margin Payload [7:0]: 88h
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7:5]: 000b
Margin Payload [4:0]: {MIndErrorSampler, MSampleReportingMethod, MIndLeftRightTiming, MIndUpDownVoltage, MVoltageSupported}
Report MNumVoltageSteps
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b through 101b
Margin Payload [7:0]: 89h
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7]: 0
Margin Payload [6:0]: MNumVoltageSteps
Report MNumTimingSteps
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7:0]: 8Ah
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7:6]: 00
Margin Payload [5:0]: MNumTimingSteps
Report MMaxTimingOffset
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b through 101b
Margin Payload [7:0]: 8Bh
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7]: 0
Margin Payload [6:0]: MMaxTimingOffset
Report MMaxVoltageOffset
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
through 101b
Margin Payload [7:0]: 8Ch
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7]: 0
Margin Payload [6:0]: MMaxVoltageOffset
Report MSamplingRateVoltage
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b through 101b
Margin Payload [7:0]: 8Dh
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7:6]: 00
Margin Payload [5:0]: {MSamplingRateVoltage [5:0]}
Report MSamplingRateTiming
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b through 101b
Margin Payload [7:0]: 8Eh
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7:6]: 00
Margin Payload [5:0]: {MSamplingRateTiming [5:0]}
ReportMSampleCount
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b through 101b
Margin Payload [7:0]: 8Fh
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7]: 0
Margin Payload [6:0]: MSampleCount
ReportMMaxLanes
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b through 101b
Margin Payload [7:0]: 90h
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7:5]: 00
Margin Payload [6:0]: MMaxLane
Set Error Count Limit
Margin Type [2:0]: 010b
Receiver Number [2:0]: 001b through 101b
Margin Payload [7:6]: 11b
Margin Payload [5:0]: Error Count Limit
 No change
Margin Type [2:0]: 001b
Receiver Number [2:0]: 001b
Margin Payload [7:6]: 11b
Margin Payload [5:0]: Error Count Limit registered by the target Receiver
Go to Normal Settings
Margin Type [2:0]: 010b
Receiver Number [2:0]: 000b through 101b
Margin Payload [7:0]: 0Fh
  • Write Committed to RX Margin Control 0 with Start Margin = 0.
  • Wait for Write Ack response from PHY or a 10 ms timeout.
  • Wait for PHY2MAC Write Committed to Margin Status or a 10 ms timeout.
Margin Type [2:0]: 010b
Receiver Number [2:0]: 001b
Margin Payload [7:0]: 0Fh
Clear Error Log
Margin Type [2:0]: 010b
Receiver Number [2:0]: 000b through 101b
Margin Payload [7:0]: 55h
  • Write Committed to RX Margin Control 0 with Error Count Reset = 1. Other fields picked up from the RX Margin Control 0 Mirror Register.
  • Wait for Write Ack response from PHY or a 10 ms timeout.
Margin Type [2:0]: 010b
Receiver Number [2:0]: 001b
Margin Payload [7:0]: 55h
Step Margin to Timing Offset to Right/Left of Default
Margin Type [2:0]: 011b
Receiver Number [2:0]: 001b through 101b
Margin Payload [7:0]: XX
If a step margin to voltage is already in progress or if a step margin to timing in the opposite direction is in progress:
  • Stop Margining by issuing Write Committed to RX Margin Control 0 with Start Margin = 0. Other fields picked up from the RX Margin Control 0 Mirror Register.
  • Wait for Write Ack response from PHY or a 10 ms timeout.
  • Wait for PHY2MAC Write Committed to Margin Status or a 10 ms timeout.
Check if RX margin command is supported.
If margin offset is supported:
  • Issue Write Uncommitted to RX Margin Control 1 with Margin Offset [6:0] = Margin Payload [5:0].
  • Issue Write Committed to RX Margin Control 0 with StartMargin: 1 and MarginTiming: 1.
  • Wait for Write Ack response from PHY or a 10 ms timeout.
  • Wait for PHY2MAC Write Committed to Margin Status or a 10 ms timeout.
Otherwise:
  • Issue NAK Status and exit.
Margin Type [2:0]: 011b
Receiver Number [2:0]: 001b
IF (Unsupported Range in Command)
Margin Payload [7:6]: 11
ELSIF (Write ACK received for Margin Command)
Margin Payload [7:6]: 01
ELSIF (PIPE MAC RX Margin Register
0 Margin Status)
Margin Payload [7:6]: 10
ELSIF (Error Count > Limit)
Margin Payload [7:6]: 00
Margin Payload [5:0]: Error Count
from RX Margin Status 2 Register
Step Margin to Voltage Offset to Up/Down of Default
Margin Type [2:0]: 100b
Receiver Number [2:0]: 001b through 110b
Margin Payload [7:0]: XX
If a step margin to timing is already in
progress or if a step margin to voltage in the opposite direction is in progress:
  • Stop Margining by issuing Write Committed to RX Margin Control 0 with Start Margin = 0. Other fields picked up from the RX Margin Control 0 Mirror Register.
  • Wait for Write Ack response from PHY or a 10 ms timeout.
  • Wait for PHY2MAC Write Committed to Margin Status or a 10 ms timeout.
Check if RX margin command is valid.
If margin offset is supported:
  • Issue Write Uncommitted to RX Margin Control 1 with Margin Offset [6:0] = Margin Payload [6:0].
  • Issue Write Committed to RX Margin Control 0 with StartMargin: 1 and MarginVoltage: 1
  • Wait for Write Ack response from PHY or a 10 ms timeout.
  • Wait for PHY2MAC Write Committed to Margin Status or a 10 ms timeout.
Otherwsie:
  • Issue NAK Status and exit.
Margin Type [2:0]: 100b
Receiver Number [2:0]: 001b
IF (Unsupported Range in Command)
Margin Payload [7:6]: 11
ELSIF (Write ACK received for Margin Command)
Margin Payload [7:6]: 01
ELSIF (PIPE MAC RX Margin Register
0 Margin Status)
Margin Payload [7:6]: 10
ELSIF (Error Count > Limit)
Margin Payload [7:6]: 00
Margin Payload [5:0]: Error Count
from RX Margin Status 2 Register
Vendor Defined
Margin Type [2:0]: 101b
Receiver Number [2:0]: 001b
Margin Payload [7:0]: Vendor Defined
 No change
Margin Type [2:0]: 101b
Receiver Number [2:0]: 001b
Margin Payload [7:0]: Vendor Defined
Margin Payload status same as
received in control register.