AXI ID Management

All inbound posted write TLPs are issued with the same TARGET_AXI_AWID so that they complete in order on the client memory subsystem. Each inbound non-posted write TLP is issued a unique TARGET_AXI_AWID so that the write responses can come back in any order. The PCIe Controller internally manages the mapping between an incoming PCIe tag of a TLP and the corresponding TARGET_AXI_AWID issued on the AXI master interface for a non-posted TLP. The PCIe Controller returns a completion TLP on receipt of a write response; it maps the incoming TARGET_AXI_BID to the corresponding PCIe tag of the TLP and sends back the completion with the appropriate tag information. The PCIe Controller cannot have more than 32 outstanding write transactions for link 0 and link 1 at any time.