Address Translation

Consider a different example where the AXI configuration TLP address map does not start at 64'h0000_0000_0000_0000. Use the PCIe Controller's address translation feature to translate the addresses to the requester id and configuration register number.

Table 1. PCIe Configuration Write and I/O Write Requests
Signal	Example 1	Example 2
MASTER_AXI_ADDR	0x4	0x0
MASTER_AXI_WSTRB	0xF0	0x0F

Example 1

In this method the AXI region has a region size of 4K bytes (lower 12 bits of AXI address). The BDF information is captured from the region registers. This method is best for smaller BDFs; that is, the PCIe configuration space is enough to handle it.

Figure 1. Outbound AXI to PCIe Configuration Space Address Translation for Configuration TLPs

Example 2

Figure 2. Outbound AXI to PCIe Configuration Space Address Translation for Configuration TLPs

The PCIe configuration write and I/O write requests have a payload size of one DWORD. The AXI address should be aligned to the first data byte enable that is provided. The data/byte enable starts from the first address location given. One DWORD of data starting from the above address is used for the configuration and I/O write payload.