L1 Substate Interface Signals
Refer to L1 Power Substates for a description of the L1 substate interface
| Signal | Direction | Width | Clock Domain | Description |
|---|---|---|---|---|
| CLKREQ_IN_N | Input | 1 | Async | This asynchronous input must be connected to the shared CLKREQ# bus, so that its state reflects the combined effect of the upstream and downstream interfaces' CLKREQ# outputs. The PCIe Controller samples this input on the positive edge of PM_CLK. |
| CLIENT_REQ_EXIT_L1_SUBSTATE | Input | 1 | PM_CLK | Client logic can trigger an explicit L1 substate exit by asserting this
signal. This signal triggers an exit from L1 substates to L0 if the PCIe Controller is already in an L1 substate. The PCIe Controller waits in L1 state for this signal to be de-asserted before
entering an L1 substate. The PCIe Controller responds to
normal L1 exit triggers while it waits for this signal to de-assert. |
| L1_PM_SUBSTATE_OUT | Output | 3 | PM_CLK |
This output provides the current state of the L1 PM substates
state machine. This output is in the PM_CLK clock domain. Its
encodings are:
000: L1-substate machine not active
001: L1.0 substate. Shown after the delay programmed in the L1 substate entry
delay field in the Low Power Debug Control Register 0
010: L1.1 substate
011: Reserved
100: L1.2.Entry substate
101: L1.2.Idle substate
110: L1.2.Exit substate
111: Reserved
|
| CLKREQ_OUT_N | Output | 1 | PM_CLK | The PCIe Controller asserts this output in the L1 substates when the core clock can be turned off. You drive this output from the PM_CLK clock domain. You can use it to enable the tri-state driver for the device's CLKREQ# output. |