RX Lane Margining

The Receiver lane margining enables system software to obtain the receiver's margin information while the link is in L0 state. The PCIe Controller:

  • Supports RX lane margining for timing and voltage in either direction from the current RX position.
  • Supports RX lane margining in endpoint and root port modes.
  • Supports RX lane margining for PHYs that implement an independent error sampler. (i.e., MIndErrorSampler ==1). MIndErrorSampler==0 is not supported.
  • Supports all lanes being margined simultaneously.
  • Supports PIPE interface revision 4.4.1 for margining.
  • Implements programmable registers in the local management space for all PHY parameters related to margining.
  • Implements the Lane Margining Capability Register Set in the PF0 configuration space at address offset 12'h920.
  • Implements logic to detect and report invalid margining commands received from host software and the PHY.

Lane margining is driven by software. Software uses the Lane Margin Control and Status register in each port (downstream or upstream) for margin control and to obtain status information for the corresponding RX associated with the port.

When the host writes a new margining command to the Lane Margin Control Register, the PCIe Controller decodes the command and performs two checks to determine whether the command is:

  • Valid:
    • Commands that do not match defined command formats are treated as invalid.
    • If the received command is invalid, the PCIe Controller discards the command and reports the error in LM register.
  • Supported (step margin commands):
    • Checks if the step margin offset is within the range supported by the device.
    • If a step margin command is unsupported, the PCIe Controller responds with NAK status in the Lane Margin Status Register. An error is not flagged in the LM registers.
Note: Refer to Exception Handling for more information on these checks.

The PCIe Controller then processes commands that are valid and supported. The PCIe Controller internally executes commands that do not require any action from the PHY, such as report commands. All other commands are delivered to the PHY over the PIPE interface.

The PCIe Controller responds to the host by updating the status appropriately in the Lane Margin Status Register. The register format is:

Table 1. Margining Lane Control and Status Register (i_margining_lane_control_status_regX)
[31:24] [23] [22] [21:19] [18:16] [15:8] [7] [6] [5:3] [2:0]
MPSTS R1 UMSTS MTSTS RNSTS MRGPAY R0 USGMOD MRGTYP RCVNUM
Margin Payload Status Reserved Usage Model Status Margin Type Status RX Number Status Margin Payload Reserved Usage Model Margin Type RX Number