Inbound PCIe to AXI Address Translation (Root Port)
The PCIe Controller performs root port inbound PCIe to AXI address translation on memory and I/O TLPs. The PCIe Controller chooses which address translation registers to use for translation based on the BAR match of the incoming TLP. There are two BARs in root port mode, so the registers are BAR0 and BAR1. Additionally, the PCIe Controller uses the BAR7 register for cases in which there are no matches. The PCIe Controller sends any address that does not match the root port BARs as a BAR7 TLP.
Each BAR register has two 32-bit registers, addr0 and
addr1. The address translation logic takes the upper bits from the root port
inbound PCIe to AXI address translation registers and takes the lower bits from the inbound
PCIe address to form the AXI address. The addr0[5:0] + 1 number of lower bits
are passed from the inbound PCIe address to AXI address. That is, the number of bits taken
from inbound PCIe address is given by the addr0[5:0] + 1 value.
| Register Name | Bits | Description | Default Value |
|---|---|---|---|
| ib_rp_[BAR]_addr1 | 31:0 | Upper [63:32] bits of the AXI address. | 32'd0 |
| ib_rp_[BAR]_addr0 | 31:8 | Lower [31:8] bits of the AXI address. | 24'd0 |
| 7:6 | Reserved | 2'd0 | |
| 5:0 | Number of address bits passed from PCIe to AXI. The PCIe Controller passes the programmed value + 1 bits from PCIe to AXI. The minimum value to be programmed into this field is 7 because the lower eight bits of the base address programmed in these registers (AXI) are replaced by zeros by the address translation logic. | 6'd0 |