Link Transition from Gen4 L0 State

The PCIe Controller only accepts margining commands when the link is in Gen4 L0 state. After the command is accepted, the PCIe Controller continues processing the command as long as the link remains in the Gen4 L0 or Recovery states.

While a margining command is being processed, if the link transitions out of the Gen4 L0 or Recovery states, the PCIe Controller:

  • Terminates all margining commands in progress.
  • Resets all state machines related to RX Lane Margining to their default states.
  • Resets all PIPE MAC registers, defined for RX Lane Margining, to their default values.
  • Leaves the margining status in Lane Margin Control and Status Register at the last valid status just before the link state transition.