Link Up
Upon power on reset, the PCIe Controller is ready for link training in 100 ms.
After the PERST# signal is deasserted, the PCIe link goes through training
and achieves link active (L0) state in another 100 ms.
- The core configuration length depends on the configuration mode. In some modes the FPGA enters user mode before the PCIe link up.
- To meet b, Efinix recommends you use SPI passive programming or SPI active programming with the following configuration:
| Programing Mode | External Clock Frequency (MHz) | Internal Oscillator CLock Divider |
|---|---|---|
| SPI active x1 | 8.04 | DIV4, DIV2, DIV1 |
| SPI active x2 | 4.04 | DIV8, DIV4, DIV2, DIV1 |
| SPI active x4 | 2.04 | DIV8, DIV4, DIV2, DIV1 |
| SPI active x8 | 1.04 | DIV8, DIV4, DIV2, DIV1 |