Integration Details

You can turn off the core clock in an L1 substate. To operate, the L1 substate requires PM_CLK. Client firmware needs to program PM_CLK. Use the Frequency Register/PM_CLK Frequency Select field in the local management register to change the PM_CLK frequency. You can only change PM_CLK frequency when LTSSM is not in L1.

By default, if there is a register access when the PCIe Controller is in the L1 substate, the PCIe Controller exits the L1 substate and responds to the register access request. The PCIe Controller moves to L0 and after servicing the register access request it goes back into the L1 substate. If the user firmware is performing polling and does not want this behavior, you can disable this feature by using the Low Power Debug and Control Register 1/ Disable Autonomous L1.x Exit upon Reg Access field in the local management space. If this field is set, the PCIe Controller gives an APB error response upon register access when it is in an L1 substate. The only reason for an error response for valid addresses at the APB interface is if a clock is not available. An error response is only available with the APB interface.