Ordering Between AXI Master Write and Read Channels

The PCIe Controller issues posted writes on the AXI master write channel, non-posted writes on the AXI master write channel, and non-posted reads on the AXI master read channel. The PCIe Controller enforces PCIe ordering between posted and non-posted reads and writes on the AXI master interface. Posted writes are always sent before of non-posted reads or writes.

Before issuing non-posted transactions on the AXI master write or AXI master read channels, the PCIe Controller ensures that previously issued posted writes have completed on the client by waiting for all TARGET_AXI_BVALID responses to come back.

On the AXI master interface, the PCIe ordering rules are followed as shown in the following tables. The columns represent a first issued transaction and the rows represent a subsequently issued transaction. The table entry indicates the ordering relationship between the two transactions. The table entries are defined as follows:

Yes—The second transaction (row) must be allowed to pass the first (column) to avoid deadlock. When blocking occurs, the second transaction must pass the first transaction. Fairness must be comprehended to prevent starvation.
Y/N—There are no requirements. The second transaction may optionally pass the first transaction or be blocked by it.
No—The second transaction must not be allowed to pass the transaction to support the producer–consumer strong ordering model.

Table 1. Inbound Ordering (Endpoint Mode)
Row Pass Column?		Posted Request (Col 2)	Non-Posted Request		Completion (Col 5)
Row Pass Column?		Posted Request (Col 2)	Read Request (Col 3)	With Data (Col 4)	Completion (Col 5)
Posted Request (Row A)		No	Yes	Yes (1)	Yes
Non-Posted Request	Read Request (Row B)	No	No	Yes	Yes
Non-Posted Request	NPR with Data (Row C)	No	Yes	No	Yes
Completion (Row D)		A: No (2) B: Y/N (3)	Yes	Yes	No (4)

Table 2. Inbound Ordering (Root Port Mode)
Row Pass Column?		Posted Request (Col 2)	Non-Posted Request		Completion (Col 5)
Row Pass Column?		Posted Request (Col 2)	Read Request (Col 3)	With Data (Col 4)	Completion (Col 5)
Posted Request (Row A)		No	Yes	N/A (1)	Yes
Non-Posted Request	Read Request (Row B)	No	No	N/A	Yes
Non-Posted Request	NPR with Data (Row C)	N/A	N/A	N/A	N/A
Completion (Row D)		A: No (2) B: Y/N (3)	Yes	N/A	No (4)

Notes:

Posted reads and writes always pass non-posted reads and writes in the transaction layer. However, a non-posted write can stall on the AXI write channel for a long time if the client cannot service the non-posted write, which in turn blocks a posted write coming in later from the link. To address this issue, the client can use the TARGET_NON_POSTED_REJ input signal to indicate that the PCIe Controller should not service non-posteds from the transaction layer's non-posted FIFO. This action allows posted transactions to go through the AXI write channel when the client cannot service non-posted read and writes.
A completion must not pass a posted request unless Row D Column 2 B applies.
An I/O or configuration write completion can pass a posted request. A completion with a relaxed ordering set can pass a posted request. A completion with an ID-based ordering set can pass a posted request if the completer ID of the completion is different from the requester ID of the posted request.
Although completions do not pass each other at the transaction layer, completions are reordered back to the AXI bus because AXI bus reads with same ID have to come in order. However, there is no relaxed ordering or ID-based ordering effect.