Configuring Registers with the APB Interface
The PCIe Controller has a 32-bit APB bus, which is accessible by the user application. The protocol is per the APB v1.0 specifications.
You configure the PCIe Controller's interfaces and features with the Efinity Interface Designer, which sets the corresponding bits in the configuration registers. The PCIe Controller uses these settings during power up or cold reset. If you want to change the setting during operation, you can set the register bits through the APB interface.
You enable the APB interface in the Interface Designer ().
| [23] | [22] | [21] | [20] | [19:12] | [11:0] |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | PCIe Physical Function 0 Registers |
| 0 | 0 | 0 | 0 | 1 | PCIe Physical Function 1 Registers |
| 0 | 0 | 0 | 0 | 2 | PCIe Physical Function 2 Registers |
| 0 | 0 | 0 | 0 | 3 | PCIe Physical Function 3 Registers |
| 0 | 0 | 0 | 0 | 4 67 | PCIe Virtual Function 0-63 Registers |
| 0 | 0 | 0 | 0 | 68 255 | Reserved |
| 0 | 0 | 0 | 1 | 0 | PCIe Local Management Registers |
| 0 | 1 | 0 | 0 | x | PCIe AXI Configuration Registers |
| 1 | 0 | 0 | 0 | 0 | PCIe Root Port Registers |
| 1 | 0 | 1 | 0 | 0 | PCIe Root Port Registers. In this mode, certain RO fields in the configuration space can be written. Please see documentation of the RC mode registers below for more information. |
These register addresses are DWORD addresses. In write operations, individual bytes can be addressed with byte-enable bits. Any addresses not defined are reserved. A configuration access from the link to a reserved address causes the PCIe Controller to return a completion packet with a UR (unsupported request) completion code. A read from the local management bus to a reserved address returns all zeros, and a write to a reserved address does not modify any of the registers. All registers (with the exception of reserved or hardwired fields) are writable from the local management bus.