Introduction

Titanium™ transceivers consist of a physical medium attachment (PMA) and a physical coding sublayer (PCS). The PMA connects the FPGA to the lane, generates the required clocks, and converts the data from parallel to serial or serial to parallel. The PCS contains the digital processing interface between the PMA and the FPGA fabric. The PCS supports SGMII, 10GBase-KR, and PCIe® Gen4 as well as PMA Direct. This user guide provides the specifications for the PCIe Controller interface.

Figure 1. Transceiver Used for PCIe

The following table shows the high-level controller configuration. It supports up to Gen4 x4, which is equivalent to a 16 Gbps lane rate or up to 64 Gbps link bandwidth.

Table 1. PCIe Controller Configuration
Parameter Setting
Operational mode Endpoint or root port1
Link width x1, x2, x4
PIPE interface fMAX
500 MHz, Gen 4
250 MHz, Gen 3
125 MHz, Gen 2
62.5 MHz, Gen 1
PCIe Controller core clock2 500 MHz
FPGA user clock (AXI interface) fMAX3 125 - 250 MHz
FPGA user data path width (AXI interface) 256 bits
AXI interface address width 64 bits
Power management clock fMAX 40 MHz

The PCIe Controller can be configured to be either endpoint (EP) or root port (RP) mode, depending on your requirements. PCIe operations initiated by the user side are driven through the AXI4 slave port; PCIe operations initiated by the host side are driven through the AXI4 master port.

Figure 2. PCIe Controller Block Diagram
Note: Refer to Appendix A: Acronyms and Abbreviations for terms used in this document.
Refer to "PCI Express Interface" in the Titanium Interfaces User Guide for configuration options.
1 Root port capabilities are limited in the Efinity® software v2024.1.
2 The PCIe Controller core clock is an internal clock.
3 This clock, AXI_CLK, is available to the user application