Message Interface FIFO Buffer

The FIFO depth can be selected to anything more than 32 with a programmable threshold for handling the message overflow (with an interrupt to the local processor when overflow is detected). You can decide which message types you require. The PCIe Controller's AXI interface contains logic to decode messages for the assertion and de-assertion of legacy interrupts.

These messages are output on the message interface the same as any other message, with the addition of assertion or deassertion of the relevant INTA_OUT, INTB_OUT, INTC_OUT, or INTD_OUT signal. The change on the relevant INTx_OUT signal occurs during the same clock cycle that the message is output on the message interface. The INTx_OUT signal levels are not changed if an assert message is received for an interrupt that is already asserted, or if a deassert message is received for an interrupt that is already deasserted. The message is output on the message interface as usual. All four interrupts are deasserted when the AXI reset is asserted and when the LINK_DOWN_RESET signal is asserted. In-bound messages from the link that are directed to the message interface (intended for the message FIFO) do not appear in the main AXI master interface.