Managing Outbound NP Outstanding Requests and Completion Responses (Endpoint)
As per the PCIe specification, an endpoint must advertise infinite credits for completion packets. Therefore, the endpoint must be ready to accept all completions it receives for all non-posted requests it initiates. The endpoint can receive responses for NP requests in multiple split completion packets.
- Stage 1 buffer—Completion FIFO RAM
- Stage 2 buffer—AXI re-ordering FIFO RAM
The stage 1 buffer performs posted vs. completion ordering checks. The PCIe Controller stores completion packets in this FIFO until the posted vs. completion ordering checks are cleared. The stage 2 buffer reorders the received split completion packets and merges them to form a single completion response for each request. This process is needed because the AXI interface cannot accept split completions.
| Parameter | Value |
|---|---|
| Maximum number of outstanding NP requests. | 128 |
| Maximum size of each NP request (MRRS). | 4096B |
| Maximum number of split completion packets received per NP request assuming each NP request is of MRRS, 64B RCB boundary and addresses are non-64B aligned. | 65 |
| Maximum number of split completion packets that can be received. | 8320 |
| Maximum number of split completion packets that can be stored in the stage 1 buffer. | 256 |
Although the stage 2 buffer can store the full size of the completion data, the stage 1 buffer is smaller and the maximum possible Completion data exceeds the stage 1 buffer storage capacity. The stage 1 buffer is temporary storage for completion packets and can only store a limited number of them. The stage 1 buffer is is not designed to store the maximum possible completion data. Therefore, the posted data must not block the completion data. The client must drain the posted data at PCIe link rate; otherwise, a completion FIFO RAM overflow can occur.
The following sections describe how the client can prevent completion FIFO overflows.
Drain Received Inbound Completion Packets at PCIe Link Rate
With this method, the client guarantees that the write data received on the PCIe Controller's AXI interface is drained at the PCIe link rate. This method ensures that the posted packets do not block the completion packets, which avoids a completion FIFO overflow.
Disable Independent Posted vs. Completion Ordering Checks
You can only use this option if the received inbound completion and posted data streams are completely independent. In this case, the client programs the local management register Disable Ordering Checks bit [30] in the i_debug_mux_control_reg register. This setting disables posted vs. completion ordering checks and decouples the two inbound data streams, and the posted packets no longer block the completion packets, which avoids a completion FIFO overflow.
Limit Outstanding NP Read Requests to Ensure FIFO Never Overflows
The client limits the total number of outstanding NP requests thereby ensuring that the completion FIFO does not overflow. Limit the number by setting the Maximum NP Outstanding Request Limit[7:0] field in the local management Debug Mux Control 2 Register. Program it based on maximum size of the NP requests and NP request address alignment as shown in the following table.
| Maximum NP Request Size (MRRS) | All NP 64B Rquest Addresses Aligned? | Programmed Value in Maximum NP Outstanding Request Limit Register |
|---|---|---|
| 64 B | Yes | 128 |
| 64 B | No | 128 |
| 128 B | Yes | 128 |
| 128 B | No | 85 |
| 256 B | Yes | 64 |
| 256 B | No | 51 |
| 512 B | Yes | 32 |
| 512 B | No | 28 |
| 1024 B | Yes | 16 |
| 1024 B | No | 15 |
| 2048 B | Yes | 8 |
| 2048 B | No | 7 |
| 4096 B | Yes | 4 |
| 4096 B | No | 3 |