Transaction Layer

On the RX side, data arrives from the data link layer over a 128-bit data path. Logic in the transaction layer decodes the packet header, performs ECRC check when the packet has a TLP digest, and aligns the payload on the data path. The data then goes through store-and-forward FIFO buffers. The PCIe Controller has separate FIFO buffers for posted, non-posted, and completion packets.

The PCIe Controller only reads a packet from the FIFO when the entire packet has been received. The decoding logic classifies packets based on their TLP header and forwards them to the appropriate modules.

The PCIe Controller processes all read/write requests to configuration registers within the transaction layer, which routes these requests to the register set of the function addressed by the request, and returns completion packets back to the link. All interrupt-related messages are processed by a separate interrupt processing module, which controls the interrupt interface. An error handling module processes error messages.

The RX flow control parameters (payload and header credit for posted, non- posted, and completion) are set based on the available space in the receive FIFO buffers. The flow control protocol ensures that the FIFO buffers do not overflow. The FIFO buffers communicate their state to the flow control module so that when the packet is forwarded out of the FIFO buffers, the corresponding credit becomes available and can be advertised to the link.

In the TX side of the transaction layer, PNP requests and completion (SC) packets arrive from the host over separate interfaces. The transaction layer multiplexes the packets, inserts the TLP header (and optionally the ECRC) and forwards them to the data link layer. The completions and messages generated are multiplexed on the same data path to the data link layer.