Function Power States

The PCIe Controller supports the PCI function power states D0 (uninitialized and active), D1, and D3hot.

By default, the PCIe Controller sets the Power Management Control Register's No Soft Reset bit for all enabled functions to 1. This setting means that the function's state is not lost when it is in the D3hot power state, and its registers do not need to be re-configured when the function is goes back to D0. The PCIe specifications recommend setting this bit for all functions.

When a root port changes an endpoint's power state form D0 to a non-D0 state, the PCIe Controller asserts POWER_STATE_CHANGE_INTERRUPT. Before asserting POWER_STATE_CHANGE_ACK, the client must ensure that no new request are issued to the PCIe link after the acknowledge is asserted. This functionality is required per the PCIe Specification.