Message TLP Access

When an outbound message access is made to an AXI region, the PCIe header fields are driven from the region register values. Only message code and message routing fields are driven through the AXI address (MASTER_AXI_AWADDR).

This example uses region two as a message region. The messages region is decoded after an access is made with an AXI address that falls between 64’h0000_0000_0020_0000 and 64'h0000_0000_002F_FFFF. The Outbound PCIe Descriptor Registers for region two must be programmed with values for message TLPs.

Note: Messages should have a minimum region size of 128 Kbytes. A bit for the message code, message routing, and message with/without data is driven through the AXI address (refer to Table 3).

For vendor-defined messages, the vendor defined message header bits [127:72] is driven through the Outbound AXI to PCIe Address Translation Registers as explained in Table 1.