SRIS Operation

The PCIe Controller supports the Separate Reference Clock Independent Spread Spectrum (SRIS) ECN. With SRIS enabled, the PCIe Controller is in SRIS mode upon power-up and can transmit and receive the SKP ordered set (OS) as required by the SRIS specifications.

Note: The SRIS feature enables a higher clock tolerance from 600 ppm to 5,600 ppm in a separate reference clock configuration. Using an incompatible clock tolerance in your system may result in an unstable L0 state or packet timeout issues. Refer to the PCIe Base Specification 3.0 or higher for more information.

In SRIS mode, the PCIe Controller transmits SKP OS (as per the SRIS and PCIe 3.0 specifications) as follows:

  • In 8b/10b encoding mode, the PCIe Controller transmits SKP OS every 128 symbols. If, due to a transmission of a large TLP, the SKP OS cannot be sent at the 128 symbol boundary, the controller accumulates all SKP OS and sends them at the end of the TLP.
  • In 128/130b encoding mode, the PCIe Controller transmits SKP OS every 32 blocks. If, due to a transmission of a large TLP, the SKP OS cannot be sent at the 32 block boundary, the controller accumulates the SKP OS and send them at the end of the TLP.

On the RX side, the PCIe Controller can handle the higher frequency SKP OS reception as mandated by the SRIS specifications.

When SRIS mode is enabled, the following two features (as defined in the PCIe 3.0 specification) are changed:

  • L0s capability is not advertised by the core in the link control register in PCI Express capability structure in the PCI compatible configuration space.
  • The modified compliance pattern at 8G or higher is different. See the SRIS ECN specification for further details.

When the SRIS control register power-on default value is changed, the L0s capability in the Link Control register should be updated accordingly via the Local Management/APB interface.

The SRIS specification has an optional feature called Lower SKP OS generation/reception. The PCIe Controller implements this feature. With this feature, the PCIe device (if needed) can revert to the non-SRIS frequency of SKP OS generation when the PCIe link is in the L0 mode. This capability is advertised in the Lower SKP OS Generation/Reception Supported Speeds Vector field of the Link Capabilities 2 register. This feature is enabled/disabled using the Enable Lower SKP OS Generation Vector field of the Link Control 3 register.

When the SRIS feature is disabled using the SRIS control register, the Lower SKP OS Generation/Reception Supported Speeds Vector field of the Link Capabilities 2 register is disabled by forcing setting the value to zero.

Note: You can enable SRIS in the Interface Designer (PCI Express block > Base tab > SRIS Enable).
During operation, you can update the setting using the APB interface. As a control and debug feature, you can enable/disable the SRIS feature using a control register in the local management space (refer to "SRIS Control Register" in the "Local Management Registers" chapter of the Titanium PCIe® Controller Registers User Guide). If you want to enable/disable SRIS mode, set/reset the SRIS Enable register field before link training begins.
Important: You cannot enable SRIS if active state power management (ASPM) is enabled.