Slot Control Register
| Bit | Description | Attributes | Implementation |
|---|---|---|---|
| 0 |
Attention Button Pressed Enable. When Set to 1b, this bit enables software
notification on an attention button pressed event (see Section 6.7.3). If the
Attention Button Present bit in the Slot Capabilities register is 0b, this bit is
permitted to be read-only with a value of 0b. Default value of this bit is 0b.
|
RW | ANDed with Attention Button Pressed Status to generate Interrupt |
| 1 | Power Fault Detected Enable. When Set, this bit enables software notification on a power fault event. If a Power Controller that supports power fault detection is not implemented, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. | RW | ANDed with Power Fault Detected Status to generate Interrupt |
| 2 | MRL Sensor Changed Enable. When Set, this bit enables software notification on a MRL sensor changed event. If the MRL Sensor Present bit in the Slot Capabilities register is Clear, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. | RW | ANDed with MRL Sensor Changed Status to generate Interrupt |
| 3 | Presence Detect Changed Enable. When Set, this bit enables software notification on a presence detect changed event. If the Hot-Plug Capable bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. | RW | ANDed with Presence Detect Changed Status to generate Interrupt |
| 4 |
Command Completed Interrupt Enable. If Command Completed notification is
supported (if the No Command Completed Support bit in the Slot Capabilities register
is 0b), when Set, this bit enables software notification when a hot-plug command is
completed by the Hot-Plug Controller. If Command Completed notification is not
supported, this bit must be hardwired to 0b. Default value of this bit is 0b.
|
RW | ANDed with Command Completed Status to generate Interrupt |
| 5 | Hot-Plug Interrupt Enable. When Set, this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is Clear, this bit is permitted to be read- only with a value of 0b. | RW | Master enable for all hot plug events interrupt generation |
| 7:6 | Attention Indicator Control. If an Attention Indicator is implemented,
writes to this field set the Attention Indicator to the written state. Reads of this
field must reflect the value from the latest write, even if the corresponding hot-plug
command is not complete, unless software issues a write without waiting, if required
to, for the previous command to complete in which case the read value is undefined.
Defined encodings are: 00b: Reserved 01b: On 10b:
Blink 11b: Off Note: The default value of this field must be one
of the non-Reserved values. If the Attention Indicator Present bit in the Slot
Capabilities register is 0b, this bit is permitted to be readonly with a value of
00b. |
RW |
Drives ATTN_INDICATOR[1:0]
output
|
| 9:8 |
Power Indicator Control. If a Power Indicator is
implemented, writes to this field set the Power Indicator to the
written state. Reads of this field must reflect the value from the
latest write, even if the corresponding hot-plug command is not
complete, unless software issues a write without waiting, if
required to, for the previous command to complete in which case the
read value is undefined. Defined encodings are:
00b: Reserved
01b: On
10b: Blink
11b: Off
Note: The default value of this field must be one of the non-Reserved
values. If the Power Indicator Present bit in the Slot Capabilities register is 0b,
this bit is permitted to be read-only with a value of 00b.
|
RW | Drives PWR_INDICATOR[1:0] output |
| 10 | Power Controller Control. If a Power Controller is implemented, this bit
when written sets the power state of the slot per the defined encodings. Reads of this
bit must reflect the value from the latest write, even if the corresponding hot- plug
command is not complete, unless software issues a write, if required to, without
waiting for the previous command to complete in which case the read value is
undefined. Note that in some cases the power controller may autonomously remove slot
power or not respond to a power-up request based on a detected fault condition,
independent of the Power Controller Control setting. The defined encodings
are: 0b: Power On 1b: Power Off If the Power Controller
Present bit in the Slot Capabilities register is Clear, then writes to this bit have
no effect and the read value of this bit is undefined. |
RW | Drives PWR_CTRL output |
| 11 |
Electromechanical Interlock Control. If an Electromechanical Interlock is
implemented, a write of 1b to this bit causes the state of the interlock to toggle.
A write of 0b to this bit has no effect. A read of this bit always returns a
0b.
|
RW | Drives EMI_CTRL output |
| 12 | Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b, this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active Reporting Capable bit is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b. | RW | ANDed with DLL State Changed Status to generate Interrupt |