AXI Master Write Operation

An AXI write transaction is a split transaction with independent address and data signals associated with the corresponding channels. The client must follow the slave protocol for the write address and data channel as described in the AXI Specification v1.0. The PCIe Controller follows the master protocol for the write address and data channel as described in the AXI specification v1.0.

The write operation starts by placing the write request parameters on the AXI master write address channel signals. The write address channel signals are qualified by asserting the TARGET_AXI_AWVALID signal. The starting write address is placed on TARGET_AXI_AWADDR. The client accepts requests when it asserts TARGET_AXI_AWREADY input to the PCIe Controller. The PCIe Controller maintains the request and its associated descriptor until it receives acknowledgement from the client.

The PCIe Controller begins to transfer the data words by placing them on the AXI master write data channel signals and asserting TARGET_AXI_WVALID. The client can pace the data transfer by controlling the TARGET_AXI_WREADY input to the PCIe Controller. The PCIe Controller keeps each data word on the TARGET_AXI_WDATA data bus until it samples the ready input as high on a positive edge of the clock. The PCIe Controller indicates the last data transfer cycle by asserting the TARGET_AXI_WLAST signal. It does not perform an early burst termination and transfers the entire burst data as indicated in the TARGET_AXI_AWLEN signal during the request cycle.

The TARGET_AXI_WSTRB[31:0] outputs to indicate the valid bytes in the data transfer cycle on the first and last cycles of the data transfer. The transfer may start and finish at any byte position in the data path. For writes of a single DWord, the byte valids may be non-contiguous, as allowed by the PCIe specification. Likewise, for two-DWORD writes, the byte valids may be non-contiguous if the starting address is aligned on an even DWORD boundary.

If the inbound TLP length is greater than the maximum AXI burst size, the PCIe Controller splits the PCIe transaction into multiple AXI write transaction with the same TARGET_AXI_AWID. This process ensures that write data read requests are committed to the client in order.