Entering L1 Substate

L1 substate entry is initiated when the link is in L1 and CLKREQ# from the upstream and downstream components are de-asserted. The PCIe Controller enters L1.1 or L1.2 depending on which substate is enabled in the L1 PM Substate Control registers.

CLKREQ_OUT_N is de-asserted in both L1 substates. When the remote device also de-asserts CLKREQ#, the core clock is turned off by the clock controller in the user domain.