L0s Power State

L0s entry and exit is an autonomous process, and has very low exit latency compared to the other link power states. In this state, the PCIe Controller automatically initiates entry into ASPM L0s if the TX is idle (i.e., no TLPs and no DLLPs to be transmitted) for a programmable time period. For the transition to occur:

  • Endpoints—ASPM L0s must be enabled in the Link Control Register of the configuration spaces of all enabled functions.
  • Root port—ASPM L0s must be enabled in the Link Control Register of the PCIe Controller root port register set.
Note: You can enable L0s in the Interface Designer (PCI Express block > Pins tab > Power Management sub-tab > Enable Power Management).
During operation, you can update the setting using the APB interface. Enable or disable active-state power management (ASPM) L0s by setting the Active State Power Management Control (bit [0]) in the Link Control and Status Register.
Important: You cannot enable active state power management (ASPM) if SRIS is enabled.

You can program the L0s entry timeout using the L0s Timeout Limit Register local management register. The transition from L0 to L0s happens after a time period programmed in the L0s Timeout Limit Register elapses with no TLP or DLLP being transmitted. Setting the L0s Timeout Limit Register to 0 disables the transition to L0s state.