End-to-End Data Protection

The PCIe protocol helps to ensure the integrity of data transferred via serial link. The Data Link Layer (DLL) provides this assurance by running a Cyclic Redundancy Check (CRC) on the integrity of Transaction Layer Packets (TLPs) and Data Link Layer Packets (DLLPs). When the DLL finds an instance of data corruption in a DLLP, the DLL initiates a retry mechanism until the data passes the CRC check. However, TLPs traveling outside the DLL (from the Transaction Layer toward the Application Layer) do not benefit from these PCIe data protection protocols. Therefore, our PCIe controller enforces additional layer of data protection in the form of a byte-wide parity check, ensuring end-to-end TLP data integrity.

Depending upon your AXI bus, customers may need to implement byte-wide odd parity in a cycle-by-cycle fashion. You generate this parity bus using the following RTL: 
genvar i;
generate
    for (i = 0; i< AXI_PCIE_SIGNAL_PAR_WIDTH; i=i+1)
        assign axi_pcie_signal_par[i] = ~(^axi_pcie_signal[i*8 +: 8]); // odd parity
    end
endgenerate
  • On the inbound path, the RTL generates parity one cycle ahead of the DLL CRC check to ensure a one-cycle overlap between the two protection methods. The controller transmits this parity data in tandem with the original data across the pipeline to the application/client logic at the controller boundary.
    • At the pcie_target_AXI interface, the controller drives parity for all bytes of pcie_target_AXI_WDATA on pcie_target_AXI_WUSER output regardless of pcie_target_AXI_WSTRB.
    • At the pcie_master_AXI interface, the controller drives parity for all bytes of pcie_master_AXI_RDATA on the pcie_master_AXI_RUSER output.
  • On the outbound path, the application/client logic provides cycle-by-cycle parity at the controller’s interface boundary (this can be either the AXI or HAL boundary, depending upon the controller configuration). The controller maintains this parity across the datapath pipeline up to the link layer. Upon receipt, the link layer generates the CRC and, one cycle later, the controller checks for parity with the data, thus ensuring a one-cycle overlap between the two protection methods.
    • At the pcie_master_AXI interface, the client must drive parity for all bytes of pcie_master_AXI_WDATA on pcie_master_AXI_WUSER, regardless of pcie_master_AXI_WSTRB.
    • At the pcie_target_AXI interface, the client must drive parity for all bytes of pcie_target_AXI_RDATA on the pcie_target_AXI_RUSER input.