Configuration Snoop Interface

The PCIe Controller has configuration space registers for each function as defined in the PCIe specifications. It supports PCI-compatible configuration space as well as PCIe extended space registers. The PCIe Controller automatically builds a linked list of capability structures, depending on the features you choose when configuring the PCI Express block in the Efinity Interface Designer.

Notice: Refer to the Titanium Interfaces User Guide for detail on configuring the PCI Express block in the Interface Designer.

During the enumeration process, the host can traverse through the PCIe Controller's linked list of structures to find out which features are supported. Root port software uses the same capability structures for control and status information. The PCIe configuration read/write TLPs are used for this purpose. The PCIe Controller maps an incoming configuration read/write TLP to a read/write access to the internal configuration space registers. The control fields of various capability structures route to different PCIe Controller layers so that the logic can use the control information as expected.

The PCIe Controller also has an optional configuration snoop interface that lets you implement your own register set in the PCIe configuration space. The interface snoops incoming configuration read/write TLPs received from the link and places them on a simple configuration snoop read/write interface. You can enable the configuration snoop interface in the Interface Designer.

Note: You obtain the actual configuration register address by multiplying the CONFIG_REG_NUM value by 4. For example, a configuration space address of 0xa00 equates to a value on CONFIG_REG_NUM of 0x280.

For a configuration write transaction, the interface places the address and data on the configuration snoop interface and asserts the CONFIG_WRITE_RECEIVED signal for one clock cycle. If the PCIe Controller implements the register being accessed, the write data is updated internally.

Figure 1. Configuration Snoop Interface Write Waveform

For configuration read transactions, the interface places the address on the configuration snoop interface and asserts the CONFIG_READ_RECEIVED signal for one clock cycle. If you want to provide the read data externally for this address, your user application must place the data on the CONFIG_READ_DATA[31:0] read data bus and assert CONFIG_READ_DATA_VALID on the first clock cycle after CONFIG_READ_RECEIVED is sampled high. The externally-provided data is sent back in the completion TLP. If the CONFIG_READ_RECEIVED input is not asserted by the user application, the PCIe Controller returns the data from its registers.

Figure 2. Configuration Snoop Interface Read Waveform

If you need more clock cycles for the configuration snoop read, you set a local management register bit. Set the Enable Extended Config Snoop Read bit in the Debug Mux Control 2 Register to 1 to change the read interface timing as shown in the following figure. If you want to provide the read data externally for this address, the user application must place the data on the CONFIG_READ_DATA[31:0] read data bus and assert CONFIG_READ_DATA_VALID within the specified number of clock cycles after CONFIG_READ_RECEIVED is sampled. If CONFIG_READ_DATA_VALID is not asserted within the window, the PCIe Controller sends the data placed in the internal registers to the completion TLP.

Figure 3. Extended Configuration Snoop Interface Read Waveform

Note: This mechanism is not intended to completely replace a capability structure. A capability structure has many control fields that the PCIe Controller uses throughout its layers for specification-mandated operation.

The control fields are routed from the internally implemented registers to the various parts of the PCIe Controller. Therefore, replacing a capability structure entirely outside the PCIe Controller is not possible.