Appendix E: Skew

The system skew has these elements.

Figure 1. System Skew

Table 1. Skew Parameters
Parameter	Description
L_RX-SKEW	Lane-to-lane skew across all lanes on a port. Prehends lane-to-lane variations due to channel and repeater delay differences.
L_CDR-SKEW	Skew inserted by clock data recovery (CDR) in the PHY. This component is added by the PHY RX clock data recovery block.
L_RM-SKEW	Skew inserted as a result of SKP addition/deletion in the rate match FIFO.

Table 2. Supported De-Skew
Generation	L_RX-SKEW¹		L_CDR-SKEW + L_RM-SKEW²		L_RX-SKEW + L_CDR-SKEW + L_RM-SKEW	Total at PIPE Interface
Generation	Symbols	ns	Symbols	ns	L_RX-SKEW + L_CDR-SKEW + L_RM-SKEW	Total at PIPE Interface
Gen1	5	20	12	48	17	20
Gen2	4	8	12	24	16	20
Gen3	6	6	12	12	18	20
Gen4	10	5	12	6	22	24

¹ The maximum possible skew at the PHY serial RX inputs per PCIe Specification.

² The skew inserted by the PHY (PMA and PCS).