AXI Slave Write Operation

An AXI write is a split transaction with independent address, data, and response phases associated with the corresponding channels. The client must follow the master protocol for the write address, data, and response channel as described in the AXI specification v1.0. The PCIe Controller follows the slave protocol for the write address, data, and response channel as described in the AXI specification v1.0.

Figure 1. AXI Slave Write Interface Waveform

The client starts a memory write operation by placing the write request parameters on the AXI slave write address channel and asserting the MASTER_AXI_AWVALID signal. Additionally, the client must place the write request PCIe TLP attributes on the master write descriptor. The PCIe Controller responds to the request by asserting the MASTER_AXI_AWREADY signal for one clock cycle. The PCIe Controller might not be able to accept the request if it does not have adequate credit to transmit the request TLP on the link or the split completion table is full (for a non-posted write).

The client begins the data transfer by placing data on the AXI slave write data channel signals and asserting the MASTER_AXI_WVALID signal. The PCIe Controller can pace the data transfer by controlling the MASTER_AXI_WREADY output. The client must keep each data word on the bus until the ready signal is sampled high. The MASTER_AXI_WSTRB inputs indicates the valid bytes in the data cycle for the first and the last data transfer. The transfer may start and finish at any byte position in the data bus, depending on the starting address alignment of the data block being written to memory. The client should assert MASTER_AXI_WLAST for the last cycle of data transfer. The client must not terminate the AXI write burst early; it should issue all write data cycles as indicated by the MASTER_AXI_AWLEN signal.

The PCIe Controller expects the byte valids to be contiguous, even for writes of a single DWORD or two DWORDs (with start address aligned to even DWORD boundary).

The PCIe Controller issues a response back to the client on the AXI slave write response channel by asserting MASTER_AXI_BVALID when a memory write transaction has been accepted by the PCIe Controller's transaction layer.

Configuration and I/O (non-posted) writes are handled in a similar manner, except that the data payload is only one DWORD long. The PCIe Controller only issues a response for I/O and configuration writes when it receives the completion back from the PCIe link.