Non-Fatal Errors

In some cases the agent that detects a non-fatal error is not the most appropriate one to determine whether the error is recoverable or not, or if it even needs a recovery action. The PCIe Controller handles the following errors as advisory non-fatal as recommended by the PCIe specification:

  • Unsupported Non-Posted Request Received
  • Unexpected Completion Received
  • Poisoned Completion TLP Received
  • Poisoned Vendor Defined Msg with Data TLP Received
  • Poisoned MWr, IOWr, or MsgD Request TLP received. Per PCIe specification section 2.7.2.2, if these requests target a control register or control structure, they must be handled as uncorrectable and not as advisory non-fatal. The PCIe Controller cannot determine if these requests target a control or a data structure in the system., Therefore, it uses the Poisoned TLP Received Advisory Non-Fatal bit in the Debug Mux Control 2 Register as follows:
    • When 0 (default), the PCIe Controller reports poisoned MWr, IOWr, MsgD as uncorrectable.
    • When 1, the PCIe Controller reports poisoned MWr, IOWr, MsgD as advisory non-fatal.
  • Completion Timeout (with Completion Timeout Advisory Non-Fatal bit set to 1 in the Debug Mux Control 2 Register). A completion timeout should always be reported as advisory non-fatal as recommended by the PCIe specification. The Completion Timeout Advisory Non-Fatal bit in the Debug Mux Control 2 Register is provided only for debugging purposes. You should not change this bit from its default value.
Table 1. Error Handling: Advisory Non-Fatal ErrorsExcept as noted, these errors result in an ERROR_OUT of FATAL/ CORRECTABLE_ERROR_OUT, based on the severity and mask.
Error Case AXI Interface Response Error Status Registers and Bits Client Action Local Interrupt
Unsupported Non-Posted Request Received Not delivered to the PCIe Controller's AXI interface. The PCIe Controller detects this error internally and responds with UR status. Unsupported Request Error Status bit in AER Uncorrectable Error Status Register. None required. No
Poisoned Completion TLP Received Reports SLVERR to the AXI slave MASTER_AXI_RRESP. Poisoned TLP Status bit in AER Uncorrectable Status Register.
Detected parity Error bit in Command Status Register.
 Client should ignore the completion data because it is poisoned. Client can retry the read request after the read data is completely received. No
Poisoned MWr, MsgD Request TLP Received
(Poisoned TLP Received Advisory Non-Fatal bit set to 1 in Debug Mux Control 2 Register)
 Not delivered to the PCIe Controller's AXI interface. The request is discarded internally. Poisoned TLP Status bit in AER Uncorrectable Status Register.
Detected parity Error bit in Command Status Register.
 None required. No
Poisoned IOWr Request TLP Received
(Poisoned TLP Received Advisory Non-Fatal bit set to 1 in Debug Mux Control 2 Register)
 Not delivered to the PCIe Controller's AXI interface. The PCIe Controller responds internally with UR status. Poisoned TLP Status bit in AER Uncorrectable Status Register.
Detected parity Error bit in Command Status Register.
 None required. No
Poisoned Vendor Defined Msg with Data TLP Received Not delivered to the PCIe Controller's AXI interface. The request is discarded internally. Poisoned TLP Status bit in AER Uncorrectable Status Register.
Detected parity Error bit in Command Status Register.
 None required. No
Completion Timeout
(Completion Timeout Advisory Non-Fatal bit set to 1 in Debug Mux Control 2 Register)
 Reports SLVERR to the AXI slave MASTER_AXI_RRESP. Completion Timeout Status bit in AER Uncorrectable Error Status Register and Local Error Status Register. Client can retry the request. Yes
Unexpected Completion Received Not delivered to the PCIe Controller's AXI interface. Unexpected Completion Received Status bit in AER Uncorrectable Error Status Register and Local Error Status Register. None required. Yes
Requester Received Completion with CA status
Error out: NIL
 Reports SLVERR to the AXI slave MASTER_AXI_RRESP. Received Target Abort Status bit in Command and Status Register. Client should ignore the read data. No
Table 2. Error Handling: Uncorrectable ErrorsThese errors result in an ERROR_OUT of FATAL/NON_FATAL_ERROR_OUT, based on the severity and mask.
Error Case AXI Interface Response Error Status Registers and Bits Client Action Local
Interrupt?
Unsupported Posted Request Received Not delivered to the PCIe Controller's AXI interface. The PCIe Controller detects this error internally and responds with UR status. Unsupported Request Error Status bit in AER Uncorrectable Error Status Register. None required. No
Poisoned CfgWr Request TLP Received Not delivered to the PCIe Controller's AXI interface. The PCIe Controller detects this error internally and responds with UR status. Poisoned TLP Status bit in AER Uncorrectable Status Register.
Detected Parity Error bit in Command Status Register.
 None required. No
Poisoned IOWr Request TLP Received
(Poisoned TLP Received Advisory Non-Fatal bit set to 0 in Debug Mux Control 2 Register)
 Not delivered to the PCIe Controller's AXI interface. The PCIe Controller detects this error internally and responds with UR status. Poisoned TLP Status bit in AER Uncorrectable Status Register.
Detected Parity Error bit in Command Status Register.
 None required. No
Poisoned MWr, MsgD Request TLP Received
(Poisoned TLP Received Advisory Non-Fatal bit set to 0 in Debug Mux Control 2 Register)
 Not delivered to the PCIe Controller's AXI interface. Request is discarded internally. Poisoned TLP Status bit in AER Uncorrectable Status Register.
Detected Parity Error bit in Command Status Register.
 None required. No
Uncorrectable RAM ECC Errors RAM ECC Errors in the RX path result in SLVERR on the AXI interface. On TX path, the AXI response can be SLVERR or OK. Uncorrectable Internal Error bit in AER Uncorrectable Error Status Register and bits in Local Error Status Register. Reset upon interrupt. Yes
Request with Unmapped TC Received Not delivered to the PCIe Controller's AXI interface. Internally handled as a malformed TLP request. Malformed TLP Received Status bit in AER Uncorrectable Error Status Register. None required. Yes
PNP RX FIFO Overflow The AXI interface does not receive the packet that caused the overflow. PNP RX FIFO Overflow bits in Local Error Status Register.
Receiver Overflow Status bit in AER Uncorrectable Error Status register.
 Reset Yes
Completion RX FIFO Overflow The AXI interface drops the completion that caused the overflow. Receiver Overflow Status bit in AER Uncorrectable Error Status Register.
Receiver Overflow Status bit in AER Uncorrectable Error Status register.
 Reset Yes
End to End Parity Error on Transmit Path If an outbound TLP has an end-to-end parity error, the TLP is dropped internally or nullified. The AXI interface does not respond with SLVERR for the same TLP at the AXI slave. Uncorrectable Internal Error bit in AER Uncorrectable Error Status Register.
End to End Parity Error in Local Error Status Register.
 Reset upon interrupt. Yes
End to End Parity Error on Receive Path If an inbound TLP has a end-to-end parity error, the PCIe Controller forwards the TLP to the AXI master with errored parity. Uncorrectable Internal Error bit in AER Uncorrectable Error Status Register.
End to End Parity Error in Local Error Status Register.
 Reset upon interrupt. Yes
ECRC Error Not delivered to the PCIe Controller's AXI interface. Request is discarded internally. ECRC Error Status bit in AER Uncorrectable Error Status Register. None required. No
Flow Control Error No effect. Flow Control Error bit in AER Uncorrectable Error Status Register and in Local Error Status Register. None required. Yes
Malformed TLP Received Not delivered to the PCIe Controller's AXI interface. Request is discarded internally. Malformed TLP Received Status bit in AER Uncorrectable Error Status Register. None required. Yes
Data Link Protocol Error Status No effect. Data Link Protocol Error Status bit in AER Uncorrectable Error Status Register. None required. No
Table 3. Error Handling: Correctable ErrorsThese errors result in an ERROR_OUT of CORRECTABLE_ERROR_OUT, based on the severity and mask.
Error Case AXI Interface Response Error Status Registers and Bits Client Action Local
Interrupt?
Header Log Overflow No effect. Header Log Overflow Status bit in AER Correctable Error Status Register. Client needs to read the header log and clear the AER error status registers. No
Correctable ECC error No effect. Corrected Internal Error Status in AER Correctable Error Status Register. None required. No
Replay Timeout No effect. Replay Timeout bit in AER Correctable Error Status Register and Local Error Status Register. None required. Yes
Replay Num Rollover No effect. Replay Num Rollover bit in AER Correctable Error Status Register and Local Error Status Register. None required. Yes
PHY Layer Errors No effect. PHY Error Detected bit in AER Correctable Error Status Register and Local Error Status Register. None required. Yes
TLP LCRC Errors No effect. Bad TLP Status bit in AER Correctable Error Status Register. None required. No
DLLP LCRC Error No effect. Bad DLLP Status bit in AER Correctable Error Status Register. None required. No
Table 4. Error Handling: Other ErrorsThese errors result in an ERROR_OUT of NIL.
Error Case AXI Interface Response Error Status Registers and Bits Client Action Local Interrupt?
Client sends SLVERR with TARGET_ AXI_RRESP SLVERR sent from TARGET_AXI_RRESP Signaled Target Abort bit in Command and Status Register. Client sends abort by sending SLVERR on TARGET_ AXI_RRESP. No
Outbound MemWr TLP Poisoned The AXI interface returns OK (2'd0) response. TLP is be transmitted on the link with the endpoint bit set. Master Data Parity Error bit in Command and Status Register. None required. No
Function-Level Reset from Host The PCIe Controller asserts FLR_IN_PROGRESS for the affected function's VF_FLR_IN_PROGRESS for the VFs. Function-Level Reset bit in PCI Express Device Control and Status Register. Client must assert FLR_DONE. No
Link Down Reset Asserts the LINK_DOWN_RESET_ OUT signal for eight clock cycles. Link Down Indication bit in AXI Configuration Registers. Client must reset the link down indication bit after clearing all outstanding requests. No