AXI Master Read Operation

An AXI read is a split transaction with independent address and data signals associated with the corresponding channels. That is, the client application can return the data for the read later. When the data for a read request becomes available, the client application transfers it using the AXI master read data channel signals. The client must send back all of the requested data in one single burst transaction.

The client must follow the slave protocol for the read address and data channel as described in the AXI Specification v1.0. The PCIe Controller follows the master protocol for the read address and data channel as described in the AXI specification v1.0.

Note: Refer to AXI Master Interface Signals for the signal descriptions.
Figure 1. AXI Master Read Waveform

The read operation starts by placing the parameters associated with the read request on the AXI master's read address channel signals. The read address channel signals are ready the TARGET_AXI_ARVALID signal is asserted. The starting read address is in on TARGET_AXI_ARADDR. The client logic accepts the requests when it asserts TARGET_AXI_ARREADY. The PCIe Controller maintains the request and its associated descriptor until it receives acknowledgement from the client.

The client initiates a read data transfer by asserting TARGET_AXI_RVALID and placing the data aligned to the request address on TARGET_AXI_RDATA. The alignment requirement is only for the first cycle of the burst transfer. Subsequent data transfer should have valid data from the least significant byte. The client should flag the last data transfer cycle by asserting TARGET_AXI_RLAST. The PCIe Controller may pace the data transfer by asserting TARGET_AXI_RREADY; in this case the client should hold the each data cycle on the TARGET_AXI_RDATA bus until the PCIe Controller asserts the ready signal.

If the inbound TLP length is greater than the maximum AXI burst size, the PCIe Controller splits the PCIe transaction into multiple AXI read transactions with the same TARGET_AXI_ARID. This process ensures that read data coming back for the read requests are in order. The PCIe Controller issues multiple split completions back to the requester on receipt of every read data from the AXI interface.

Note: The AXI master interface does not support read data interleaving.