About the PLL Interface

Topaz FPGAs have PLLs to synthesize clock frequencies. The PLLs are located in the corners of the FPGA. You can use the PLL to compensate for clock skew/delay via external or internal feedback to meet timing requirements in advanced applications. The PLL reference clock has up to four sources. You can dynamically select the PLL reference clock with the CLKSEL port. (Hold the PLL in reset when dynamically selecting the reference clock source.)

The PLL consists of a pre-divider counter (N counter), a feedback multiplier counter (M counter), a post-divider counter (O counter), and output dividers (C).

At startup, Efinix recommends that you hold the PLL in reset until the PLL's reference clock source is stable.

Note: You can cascade PLLs. To avoid the PLL losing lock, Efinix recommends that you do not cascade more than two PLLs.

At startup, Efinix recommends resetting all cascaded PLLs. Hold the first PLL in reset until the PLL's reference clock source is stable. Hold the cascaded PLLs in reset until the previous PLL is locked.

Cascaded PLLs do not need a 50% duty cycle on the reference clock. However, the clock needs to meet the PLL minimum pulse width as specified in the data sheet.

The counter settings define the PLL output frequency:


Local and Core Feedback Mode	Where:
F_PFD = F_IN / N F_VCO = (F_PFD x M x O x C_FBK ) ¹ F_PLL = F_VCO / O F_OUT = (F_IN x M x C_FBK) / (N x C)	F_VCO is the voltage control oscillator frequency F_PLL is the post-divider PLL VCO frequency F_OUT is the output clock frequency F_IN is the reference clock frequency F_PFD is the phase frequency detector input frequency O is the post-divider counter C is the output divider

Note: Refer to the PLL Timing and AC Characteristics for F_VCO, F_OUT, F_IN, F_PLL, and F_PFD values.

Table 1. PLL Signals (Interface to FPGA Fabric)
Signal	Direction	Description
CLKIN[3:0]	Input	Reference clocks driven by I/O pads or core clock tree.
CLKSEL[1:0]	Input	You can dynamically select the reference clock from one of the clock in pins.
RSTN	Input	Active-low PLL reset signal. When asserted, this signal resets the PLL; when de-asserted, it enables the PLL. De-assert only when the CLKIN signal is stable. Connect this signal in your design to power-up or reset the PLL. Assert the RSTN pin for a minimum pulse of 10 ns to reset the PLL. Assert RSTN when dynamically changing the selected PLL reference clock.
FBK	Input	Connect to a clock out interface pin when the PLL is in when the PLL is not in internal feedback mode.
CLKOUT0 CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4	Output	PLL output. You can route these signals as input clocks to the core's GCLK network. Tz50: CLKOUT4 can only feed the top or bottom regional clocks. Tz50: All PLL outputs lock on the negative clock edge. The Interface Designer inverts the clock polarity on the leaf cells by default (Invert Output Clock option unchecked). Check the option if you are using the clock to drive core logic. You can use CLKOUT0 only for clocks with a maximum frequency of 4x (integer) of the reference clock. If all your system clocks do not fall within this range, you should dedicate one unused clock for CLKOUT0.
LOCKED	Output	Goes high when PLL achieves lock; goes low when a loss of lock is detected. Connect this signal in your design to monitor the lock status. This signal is not synchronized to any clock and the minimum high or low pulse width of the lock signal may be smaller than the CLKOUT’s period.
SHIFT[2:0]	Input	(Optional) Dynamically change the phase shift of the output selected to the value set with this signal. Possible values from 000 (no phase shift) to 111 (3.5 F_PLL cycle delay). Each increment adds 0.5 cycle delay.
SHIFT_SEL[4:0]	Input	(Optional) Choose the output(s) affected by the dynamic phase shift.
SHIFT_ENA	Input	(Optional) When high, changes the phase shift of the selected PLL(s) to the new value.

Notice: Refer to the device data sheet for the list of PLL reference clock assignments.

Table 2. PLL Interface Designer Settings
Parameter	Choices	Notes
Instance Name	User defined
PLL Resource		The resource listing depends on the FPGA you choose.
Output Clock Inversion	On, off	Turn on to invert each output clock individually.
Connection Type	gclk, rclk	Output clocks 3 and 4 can feed the global clock network (default). Some PLLs can also drive the regional clock network; see "Driving the Regional Network" in the data sheet for details.
Clock Source	External	PLL reference clock comes from an external pin. Select the available external clock.
	Dynamic	PLL reference clock comes from four possible sources (external and core), and are controlled by the clock select bus. Specify the clock selector pin name and core clock pin name
	Core	PLL reference clock comes from the core. Specify the core clock pin name.
Automated Clock Calculation		Pressing this button launches the PLL Clock Calculation window. The calculator helps you define PLL settings in an easy-to-use graphical interface. Refer to Using the PLL Clock Calculator for more details.

¹ (M x O x C_FBK) must be ≤ 255.